AD603
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GPOS
GNEG
VINP
1
2
3
4
8
7
6
5
VPOS
VOUT
VNEG
FDBK
GPOS
GNEG
VINP
1
2
3
4
8
7
6
5
VPOS
VOUT
VNEG
FDBK
AD603
AD603
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
COMM
COMM
Figure 2. 8-Lead SOIC Pin Configuration
Figure 3. 8-Lead CERDIP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
GPOS
GNEG
VINP
COMM
FDBK
VNEG
Gain Control Input High (Positive Voltage Increases Gain).
Gain Control Input Low (Negative Voltage Increases Gain).
Amplifier Input.
Amplifier Ground.
Connection to Feedback Network.
Negative Supply Input.
VOUT
VPOS
Amplifier Output.
Positive Supply Input.
Rev. I | Page 5 of 24
ROCHESTER [ Rochester Electronics ]
