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5962-8770103RA 参数 Datasheet PDF下载

5962-8770103RA图片预览
型号: 5962-8770103RA
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.18 us SETTLING TIME, 8-BIT DAC, CDIP20, 0.300 INCH, GLASS SEALED, SKINNY, CERDIP-20]
分类和应用: 输入元件转换器
文件页数/大小: 11 页 / 878 K
品牌: ROCHESTER [ Rochester Electronics ]
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AD7528  
V
A
IN  
(± 10V)  
Table I. Unipolar Binary Code Table  
1
R1  
DAC Latch Contents Analog Output  
1
R2  
MSB  
LSB  
(DAC A or DAC B)  
V
DD  
2
R
A
C1  
FB  
255  
VIN  
DB0  
1 1 1 1 1 1 1 1  
1 0 0 0 0 0 0 1  
1 0 0 0 0 0 0 0  
0 1 1 1 1 1 1 1  
0 0 0 0 0 0 0 1  
0 0 0 0 0 0 0 0  
INPUT  
BUFFER  
DATA  
INPUTS  
256  
V
A
DAC A  
OUTA  
AGND  
LATCH  
OUT  
DB7  
129  
VIN  
AGND  
256  
AD7528  
1
VIN  
2
128  
256  
R4  
DAC A/  
VIN  
VIN  
VIN  
VIN  
= −  
DAC B  
2
CONTROL  
LOGIC  
R
B
C2  
FB  
CS  
127  
256  
WR  
OUT B  
LATCH  
DAC B  
R3  
V
B
OUT  
DGND  
1
256  
AGND  
1
0
256  
= 0  
V
B
IN  
(± 10V)  
NOTES:  
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.  
SEE TABLE III FOR RECOMMENDED VALUES.  
C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN  
USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.  
1
256  
28  
V
(
)
=
V
(
Note: 1 LSB =  
)
)
(
IN  
IN  
2
Figure 4. Dual DAC Unipolar Binary Operation  
(2 Quadrant Multiplication); See Table I  
V
A
IN  
Table II. Bipolar (Offset Binary) Code Table  
DAC Latch Contents Analog Output  
(± 10V)  
R5  
20k⍀  
2
R6  
1
R1  
20k⍀  
MSB  
LSB  
(DAC A or DAC B)  
2
R7  
V
A
A2  
OUT  
1
R2  
10k⍀  
127  
+VIN  
1 1 1 1 1 1 1 1  
1 0 0 0 0 0 0 1  
1 0 0 0 0 0 0 0  
0 1 1 1 1 1 1 1  
0 0 0 0 0 0 0 1  
0 0 0 0 0 0 0 0  
V
3
DD  
128  
C1  
R
A
R11  
5k⍀  
FB  
DB0  
INPUT  
BUFFER  
DATA  
INPUTS  
A1  
AGND  
DAC A  
OUTA  
AGND  
LATCH  
DB7  
0
AGND  
AD7528  
1
R4  
B
DAC A/  
1
VIN  
DAC B  
3
CONTROL  
LOGIC  
R
C2  
FB  
CS  
128  
WR  
R8  
20k⍀  
LATCH  
DAC B  
R3  
OUT B  
AGND  
A3  
127  
VIN  
2
R9  
DGND  
128  
10k⍀  
128  
VIN  
2
A4  
V
B
R10  
OUT  
1
128  
20k⍀  
R12  
1
128  
27  
V
(
)
=
V
(
5k⍀  
V
B
Note: 1 LSB =  
)
)
(
IN  
IN  
IN  
AGND  
(± 10V)  
NOTES:  
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.  
SEE TABLE III FOR RECOMMENDED VALUES.  
ADJUST R1 FOR V  
ADJUST R3 FOR V  
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS  
R6, R7 AND R9, R10.  
C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED  
IF A1/A3 IS A HIGH SPEED AMPLIFIER.  
A = 0V WITH CODE 10000000 IN DAC A LATCH.  
B = 0V WITH CODE 10000000 IN DAC B LATCH.  
OUT  
OUT  
2
3
Table III. Recommended Trim Resistor  
Values vs. Grade  
Trim  
Resistor  
Figure 5. Dual DAC Bipolar Operation  
(4 Quadrant Multiplication); See Table II  
J/A/S  
K/B/T  
L/C/U  
R1; R3  
R2; R4  
1 k  
330  
500  
150  
200  
82  
REV. B  
–5–