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5962-87701022A 参数 Datasheet PDF下载

5962-87701022A图片预览
型号: 5962-87701022A
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.18 us SETTLING TIME, 8-BIT DAC, CQCC20, CERAMIC, LCC-20]
分类和应用: 输入元件转换器
文件页数/大小: 11 页 / 878 K
品牌: ROCHESTER [ Rochester Electronics ]
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AD7528  
APPLICATIONS INFORMATION  
Application Hints  
To ensure system performance consistent with AD7528 specifi-  
cations, careful attention must be given to the following points:  
ship between input frequency and channel to channel isolation.  
Figure 7 shows a printed circuit layout for the AD7528 and the  
AD644 dual op amp which minimizes feedthrough and crosstalk.  
SINGLE SUPPLY APPLICATIONS  
1. GENERAL GROUND MANAGEMENT: AC or transient  
voltages between the AD7528 AGND and DGND can cause  
noise injection into the analog output. The simplest method  
of ensuring that voltages at AGND and DGND are equal is  
to tie AGND and DGND together at the AD7528. In more  
complex systems where the AGND–DGND intertie is on the  
backplane, it is recommended that diodes be connected in  
inverse parallel between the AD7528 AGND and DGND  
pins (1N914 or equivalent).  
2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a  
code-dependent output resistance which in turn causes a  
code-dependent amplifier noise gain. The effect is a code-  
dependent differential nonlinearity term at the amplifier  
output which depends on VOS (VOS is amplifier input offset  
voltage). This differential nonlinearity term adds to the R/2R  
differential nonlinearity. To maintain monotonic operation, it  
is recommended that amplifier VOS be no greater than 10% of  
1 LSB over the temperature range of interest.  
The AD7528 DAC R-2R ladder termination resistors are con-  
nected to AGND within the device. This arrangement is par-  
ticularly convenient for single supply operation because AGND  
may be biased at any voltage between DGND and VDD. Figure  
8 shows a circuit which provides two +5 V to +8 V analog out-  
puts by biasing AGND +5 V up from DGND. The two DAC  
reference inputs are tied together and a reference input voltage  
is obtained without a buffer amplifier by making use of the  
constant and matched impedances of the DAC A and DAC B  
reference inputs. Current flows through the two DAC R-2R  
ladders into R1 and R1 is adjusted until the VREF A and VREF  
B
inputs are at +2 V. The two analog output voltages range from  
+5 V to +8 V for DAC codes 00000000 to 11111111.  
V
= +15V  
DD  
DAC A  
V
A = +5V TO +8V  
B = +5V TO +8V  
OUT  
DB0  
DB7  
DATA  
INPUTS  
SUGGESTED  
OP AMP:  
AD644  
CS  
3. HIGH FREQUENCY CONSIDERATIONS: The output  
capacitance of a CMOS DAC works in conjunction with the  
amplifier feedback resistance to add a pole to the open loop  
response. This can cause ringing or oscillation. Stability can  
be restored by adding a phase compensation capacitor in  
parallel with the feedback resistor.  
AD7528  
DAC B  
WR  
DAC A/DAC B  
V
OUT  
2 VOLTS  
R1  
10k⍀  
AD584J  
V
R2  
1k⍀  
DD  
GND  
DYNAMIC PERFORMANCE  
The dynamic performance of the two DACs in the AD7528 will  
depend upon the gain and phase characteristics of the output  
amplifiers together with the optimum choice of the PC board  
layout and decoupling components. Figure 6 shows the relation  
Figure 8. AD7528 Single Supply Operation  
Figure 9 shows DAC A of the AD7528 connected in a positive  
reference, voltage switching mode. This configuration is useful  
in that VOUT is the same polarity as VIN allowing single supply  
operation. However, to retain specified linearity, VIN must be in  
the range 0 V to +2.5 V and the output buffered or loaded with  
a high impedance, see Figure 10. Note that the input voltage is  
connected to the DAC OUT A and the output voltage is taken  
from the DAC VREF A pin.  
–100  
T
= +25؇C  
A
V
V
= +15V  
–90  
–80  
–70  
–60  
–50  
DD  
= 20V PEAK TO PEAK  
IN  
V
OUT  
V
(0V TO +2.5V)  
IN  
V
A
REF  
V
DD  
DAC A  
OUT A  
+15V  
AD7528  
20k  
50k  
100k  
200k  
500k  
1M  
INPUT FREQUENCY – Hz  
Figure 9. AD7528 in Single Supply, Voltage Switching Mode  
Figure 6. Channel-to-Channel Isolation  
3
PIN 8 OF TO-5 CAN (AD644)  
AD644  
V+  
T
= +25؇C  
A
V
= +15V  
DD  
2
1
V–  
NONLINEARITY  
AGND  
AD7528 PIN 1  
C1 LOCATION  
V
*NOTE  
INPUT SCREENS  
TO REDUCE  
FEEDTHROUGH.  
LAYOUT SHOWS  
COPPER SIDE  
C2 LOCATION  
A*  
B*  
REF  
V
DIFFERENTIAL  
NONLINEARITY  
V
DD  
REF  
WR  
CS  
DGND  
DAC A/DAC B  
MSB  
AD7528  
(i.e., BOTTOM VIEW).  
LSB  
2.5  
3
3.5  
4
4.5  
V
5
5.5  
6
6.5  
7
7.5  
A – Volts  
IN  
Figure 7. Suggested PC Board Layout for AD7528 with  
AD644 Dual Op Amp  
Figure 10. Typical AD7528 Performance in Single Supply  
Voltage Switching Mode (K/B/T, L/C/U Grades)  
–6–  
REV. B