Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
OE , OE
1
Output Enable Input
Data Inputs
1.0/1.0
1.0/1.0
2
b
D –D
0
20 mA/ 0.6 mA
7
b
O –O
0
Data Outputs, TRI-STATE 600/106.6 (80)
12 mA/64 mA (48 mA)
7
Function Table
Outputs
Functional Description
The ’F827 and ’F828 are line drivers designed to be em-
ployed as memory address drivers, clock drivers and bus-
oriented transmitters/receivers which provide improved PC
board density. The devices have TRI-STATE outputs con-
trolled by the Output Enable (OE) pins. The outputs can sink
64 mA (48 mA mil) and source 15 mA. Input clamp diodes
limit high-speed termination effects.
Inputs
O
Function
n
OE
D
n
’F827
’F828
L
L
H
H
L
L
H
Z
Transparent
Transparent
High Z
L
H
X
Z
e
e
e
e
H
L
HIGH Voltage level
LOW Voltage Level
High Impedance
Immaterial
Z
X
Logic Diagrams
’F827
TL/F/9598–4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
’F828
TL/F/9598–11
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
ROCHESTER [ Rochester Electronics ]
