Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
7
LE
Latch Enable Input (Active HIGH)
TRI-STATE Output Enable Input
(Active LOW)
OE
b
1.0/1.0
20 mA/ 0.6 mA
b
O –O
0
TRI-STATE Latch Outputs
150/40(33.3)
3 mA/24 mA (20 mA)
7
Functional Description
The ’F573 contains eight D-type latches with 3-state output
Function Table
buffers. When the Latch Enable (LE) input is HIGH, data on
the D inputs enters the latches. In this condition the latch-
n
Inputs
LE
Outputs
O
es are transparent, i.e., a latch output will change state each
time its D input changes. When LE is LOW the latches store
the information that was present on the D inputs a setup
time preceding the HIGH-to-LOW transition of LE. The 3-
state buffers are controlled by the Output Enable (OE) input.
When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfer with entering new data into
the latches.
OE
D
L
L
H
H
L
H
L
H
L
L
X
X
O
0
H
X
Z
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
O
e
Value stored from previous clock cycle
0
Logic Diagram
TL/F/9566–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
ROCHESTER [ Rochester Electronics ]
