Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
HIGH/LOW
Output I /I
OH OL
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
S –S
0
Polynomial Select Inputs
Check Word Generate Input
Serial Data/Check Word
Data Input
1.0/0.67
1.0/0.67
3
CWG
b
b
b
5.7 mA( 2 mA)/8 mA (4 mA)
D/CW
D
285(100)/13.3(6.7)
1.0/0.67
b
20 mA/ 0.4 mA
ER
RO
CP
Error Output
*/26.7(13.3)
285(100)/13.3(6.7)
1.0/0.67
*/16 mA (8 mA)
b
Register Output
Clock Pulse
5.7 mA( 2 mA)/8 mA (4 mA)
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
b
20 mA/ 0.4 mA
SEI
RFB
MR
P
Serial Expansion Input
Register Feedback
Master Reset
1.0/0.67
1.0/0.67
1.0/0.67
Preset
1.0/0.67
*Open Collector
Functional Description
The ’F402 Serial Data Polynomial Generator/Checker is an
expandable 16-bit programmable device which operates on
serial data streams and provides a means of detecting
transmission errors. Cyclic encoding and decoding schemes
for error detection are based on polynomial manipulation in
modulo arithmetic. For encoding, the data stream (message
polynomial) is divided by a selected polynomial. This divi-
sion results in a remainder (or residue) which is appended to
the message as check bits. For error checking, the bit
stream containing both data and check bits is divided by the
same selected polynomial. If there are no detectable errors,
this division results in a zero remainder. Although it is possi-
ble to choose many generating polynomials of a given de-
gree, standards exist that specify a small number of useful
polynomials. The ’F402 implements the polynomials listed in
Table I by applying the appropriate logic levels to the select
XOR gates. The Check Word Generate (CWG) must be held
HIGH while the data is being entered. After the last data bit
is entered, the CWG is brought LOW and the check bits are
shifted out of the register(s) and appended to the data bits
(no external gating is needed).
To check an incoming message for errors, both the data
and check bits are entered through the D Input with the
CWG Input held HIGH. The Error Output becomes valid af-
ter the last check bit has been entered into the ’F402 by a
LOW-to-HIGH transition of CP, with the exception of the
Ethernet polynomial (see Applications paragraph). If no de-
tectable errors have occurred during the data transmission,
the resultant internal register bits are all LOW and the Error
Output (ER) is HIGH. If a detectable error has occurred, ER
is LOW. ER remains valid until the next LOW-to-HIGH tran-
sition of CP or until the device has been preset or reset.
pins S , S , S and S .
2
0
1
3
A HIGH on the Master Reset Input (MR) asynchronously
clears the entire register. A LOW on the Preset Input (P)
asynchronously sets the entire register with the exception
of:
The ’F402 consists of a 16-bit register, a Read Only Memory
(ROM) and associated control circuitry as shown in the
Block Diagram. The polynomial control code presented at
inputs S , S , S and S is decoded by the ROM, selecting
2
0
1
3
1 The Ethernet residue selection, in which the registers
containing the non-zero residue are cleared;
the desired polynomial or part of a polynomial by establish-
ing shift mode operation on the register with Exclusive OR
(XOR) gates at appropriate inputs. To generate the check
bits, the data stream is entered via the Data Inputs (D), us-
ing the LOW-to-HIGH transition of the Clock Input (CP). This
data is gated with the most significant Register Output (RO)
via the Register Feedback Input (RFB), and controls the
2 The 56th order polynomial, in which the 8 least significant
register bits of the least significant device are cleared;
and,
e
3 Register S 0, in which all bits are cleared.
2
ROCHESTER [ Rochester Electronics ]
