August 1995
54F/74F280
9-Bit Parity Generator/Checker
General Description
Features
Y
Guaranteed 4000V minimum ESD protection
The ’F280 is a high-speed parity generator/checker that ac-
cepts nine bits of input data and detects whether an even or
an odd number of these inputs is HIGH. If an even number
of inputs is HIGH, the Sum Even output is HIGH. If an odd
number is HIGH, the Sum Even output is LOW. The Sum
Odd output is the complement of the Sum Even output.
Package
Commercial
74F280PC
Military
Package Description
Number
N14A
J14A
14-Lead (0.300 Wide) Molded Dual-In-Line
×
54F280DM (Note 2)
14-Lead Ceramic Dual-In-Line
74F280SC (Note 1)
74F280SJ (Note 1)
M14A
M14D
W14B
E20A
14-Lead (0.150 Wide) Molded Small Outline, JEDEC
×
14-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
54F280FM (Note 2)
54F280LM (Note 2)
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
SCX and SJX.
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DMQB, FMQB and LMQB.
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9512–3
IEEE/IEC
TL/F/9512–1
TL/F/9512–2
TL/F/9512–5
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9512
RRD-B30M115/Printed in U. S. A.
ROCHESTER [ Rochester Electronics ]
