Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
S
Common Data Select Input
1.0/1.0
1.0/1.0
OE
TRI-STATE Output Enable Input (Active LOW)
Data Inputs from Source 0
I
I
–I
0a 0d
1.0/1.0
b
–I
1a 1d
Data Inputs from Source 1
1.0/1.0
20 mA/ 0.6 mA
b
Z –Z
a
TRI-STATE Multiplexer Outputs
150/40 (33.3)
3 mA/24 mA (20 mA)
d
Functional Description
Truth Table
The ’F257A is a quad 2-input multiplexer with TRI-STATE
outputs. It selects four bits of data from two sources under
control of a Common Data Select input. When the Select
Output
Enable
Select
Data
Output
Z
Input
Inputs
input is LOW, the I inputs are selected and when Select is
0x
OE
S
I
0
I
1
HIGH, the I inputs are selected. The data on the selected
1x
H
L
L
L
L
X
H
H
L
X
X
X
L
X
L
Z
L
inputs appears at the outputs in true (non-inverted) form.
The device is the logic implementation of a 4-pole, 2-posi-
tion switch where the position of the switch is determined by
the logic levels supplied to the Select input. The logic equa-
tion for the outputs is shown below:
H
X
X
H
L
L
H
H
e
a
I
on
Z
n
OE (I
#
S
S)
#
#
n
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
e
e
e
When the Output Enable input (OE) is HIGH, the outputs are
forced to a high impedance OFF state. If the outputs are
tied together, all but one device must be in the high imped-
ance state to avoid high currents that would exceed the
maximum ratings. Designers should ensure the Output En-
able signals to TRI-STATE devices whose outputs are tied
together are designed so there is no overlap.
X
Z
High Impedance
Logic Diagram
TL/F/9507–4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
ROCHESTER [ Rochester Electronics ]
