RT7205A
be advertised to an Upstream Facing Port (UFP) as default
USB current, 1.5A, and 3.0A, respectively.
The OVP pin is pulled low when output over-voltage
condition (register-programmable : 115%, 120%, 125%)
occurs. By way of an optocoupler, it can shut down the
primary-side controller (for example, RT7752).
5V
CC1I
DIEN
BLD/OVP
10-bit
MCU
DOL
CC1/CC2
ADC
DI
Figure 5. Interface of BLD and OVP Pins
Figure 4. Interface of CC1 and CC2
SR Control
To improve theAC-DC converter's efficiency, the RT7205A
includes a SR controller, which has proprietary auto-
tracking function to minimize dead time between the
conduction intervals of the SR MOSFET and the main
switch MOSFET, while it can still ensure safe operation
in bothDCM and CCM conditions and even in a wide output
range. To prevent the on-time overlap of the main switch
MOSFET and the SR MOSFET, the SR controller will be
temporarily turned off under conditions of load transition,
output voltage transition, output short circuit, or low output
or input voltages with programmable thresholds. At light
load or no load condition, the SR controller will also be
disabled to reduce power consumption.
Open-Drain Drivers for BLD and OVP Pins
The BLD and OVP pins with their specific functions are
driven by open-drain drivers, as shown in Figure 5 and
explained below.
The BLD pin is used as a bleeder to help discharge the
output capacitor to Vsafe5V upon the detachment of a
connected device, or to a lower desired output voltage
level upon a UFP request, such as from 12V to 5V. A
resistor is connected between VOUT and the BLD pin and
a power resistor can be used for better power dissipation
capability.
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7205A-00 February 2018
www.richtek.com
7
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
