RT6010
V
IN
0.22µF
0.22µF
120µF/450V
0.22µF
0.22µF
5V
12V
5V
50k
D4
D2
D1
D3
10µF
1k
4.7mH
4.7mH
4.7mH
RT6010 (Stage_1)
RT6010 (Stage_2)
4.7mH
VCC
EN
VCC
EN
EN
Q1
5
GATE1
CS1
GATE1
CS1
Q3
5
DIM/PWM_IN
DIM/PWM_IN
22nF
FAULT
DPS
FAULT
DPS
High : Disable SPD Function
Low : Support SPD
Q2
5
Q4
5
GATE2
GATE2
F_DELAY
F_DELAY
CS2
CS2
10nF
10nF
D_OSC
D_OSC
PWM_OUT
PWM_OUT
RT_OUT
VSS RT
RT_OUT
VSS RT
10nF
180k
Stage_3 DIM/PWM_IN
Stage_3 RT
FAULT
Figure 3. Synchronization for Multiple Channel_Analog
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
2
3
VCC
Power Supply for PWM Controller.
Dimming PWM Pulse Input orAnalog Voltage Input.
Constant off time setting by connecting proper resistor to VSS.
DIM/PWM_IN
RT
For analog dimming, D_OSC should be connected to a capacitor to generate
dimming triangle oscillator that is compared with DIM/PWM_IN DC voltage level to
generate PWM dimming pulse. For digital dimming, D_OSC should be connected
to VSS.
4
D_OSC
Define FAULT pin output delay by connecting to a proper capacitor to prevent false
trigger for UVP and OTP.
5
F_DELAY
6
7
Open drain output fault including UVP, OVP, and OTP (Active Low).
No Internal Connection.
FAULT
NC
8
DPS
Smart Phase Shift Dimming Disable Pin. Pull DPS high to disable function.
Channel 1 Current Sense Input.
9
CS1
10
11
12
GATE1
GATE2
CS2
Channel 1 Current Gate Driver Output.
Channel 2 Current Gate Driver Output.
Channel 2 Current Sense Input.
Chip Enable (Active High). Enable PWM system, prefer connect to VIN resistive
voltage divider to guarantee VIN power ready to prevent from PWM malfunction.
13
EN
14
15
16
RT_OUT
PWM_OUT
VSS
Output for the next RT6010 RT.
SPD (Smart Phase Shift Dimming) output for slave to synchronize dimming phase
shift.
Ground.
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6010-00 March 2012
www.richtek.com
3
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