RT5072
Functional Pin Description
Pin No.
Pin Name
Pin Function
Wake-Up Impulse Push Pull Output. If VIN or BAT plug in, the WAKE pin generates one
90ms-width high pulse to notify micro processor.
1
WAKE
Power Output of CH1. To make CH1 stable, the power path from the PVD1 pin to its
output capacitors must be as short (1mm is better) and wide as possible to reduce its
parasitic inductance. The output capacitor must be ceramic capacitor (20F).
2
PVD1
LX1
3
4
5
Switch Node of CH1.
2nd Charger Status Indicator (Open-Drain Output).
Feedback Input Pin of CH7 in Step-Up Mode or Current Regulator Mode
CHG2
FB7
Power Output Pin of CH7 in Step-Up or Power Input Pin of CH7 in Current Regulator
Mode.
6
7
PVD7
LX7
Switch Node of CH7 in Step-Up Mode.
LX7 initial voltage determine CH7 operation mode.
8
Charger Status Indicator Output (Open-Drain Output).
Power Output of CH6.
CHG
VO6
PVD6
FB4
SEQ
LX4
9
10
11
12
13
14
Power Input of CH6.
Feedback Voltage Input of CH4.
Power Sequence Selection for CH1 to CH4.
Switch Node of CH4.
EN
Enable Control Input of Power Converter Unit.
Power Input of CH4 and CH5. To avoid the crosstalk between CH4 and CH5, the power
path from the PVD45 pin to its input capacitors must be as short (1mm is better) and
wide as possible to reduce its parasitic inductance. The input capacitance must be
10F with low ESR.
15
16
PVD45
LX5
Switch Node of CH5.
Interrupt Indicator Open-Drain Output. If events of NoBAT, THR, EOC, Battery
Temperature Change (TS_METER), PGOOD, SAFE, VIN DPM, or Charge Type
Detection Finishing (CHGRUN) happen, the output INT goes low and the INT bit in I2C
register bank 0x9 is set to be “1”. After INT bit is written to be “0”, INT goes high.
17
INT
Output Voltage Sense or Feedback Voltage Input of CH5. The function is
I2C register.
selected by
18
VO5/FB5
19
20
21
22
23
24
25
26
27
PVD8
SDA
SCL
Power Input of CH8.
Data Signal of I2C Interface.
Clock Signal of I2C Interface.
Power Output of CH8.
VO8
FB2
Feedback Voltage Input of CH2.
Power Output of CH2.
VO2
LX2B
LX2A
PVD2
Switch Node B of CH2.
Switch Node A of CH2.
Power Input of CH2.
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4
DS5072-00 March 2015