RT3663BC
Operation
Error Amplifier
MUX and ADC
The Error amplifier generates COMP/COMPA signal by
the difference between VSET/VSETAand FB/FBA.
The MUX supports the inputs from SET1, SET2, SET3,
OFS, OFSA, IMON, IMONA, VSEN, or VSENA. TheADC
converts these analog signals to digital codes for reporting
or performance adjustment.
Offset Cancellation
This block cancels the output offset voltage from voltage
ripple and current ripple to achieve accurate output voltage.
SVI2 Interface
The SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with CPU. The RT3663BC's performance
and behavior can be adjusted by commands sent by CPU
or platform.
PWM CMPx
The PWM comparator compares COMP signal and current
feedback signal to generate a signal for TONGENx.
TONGEN/TONGENA
UVLO
This block generates an on-time pulse which high interval
is based on the on-time setting and current balance.
The UVLO detects the VCC pin voltages for under voltage
lockout protection and power on reset operation.
Current Balance
Loop Control Protection Logic
Per-phase current is sensed and adjusted by adjusting
on-time of each phase to achieve current balance for each
phase.
Loop control protection logic detects ENand UVLO signals
to initiate soft-start function and control PGOOD,
PGOODA and OCP_L signals after soft-start is finished.
When dual OCP event occurs, the OCP_L pin voltage is
pulled low.
OC/OV/UV/NV
VSEN/VSENA and output current are sensed for over-
current, over-voltage, under-voltage, and negative-voltage
protections.
DAC
The DAC receives VID codes from the SVI2 control logic
to generate an internal reference voltage (VSET/VSETA)
for controller.
RSET/RSETA
The Ramp generator is designed to improve noise immunity
and reduce jitter.
Soft-Start and Slew-Rate Control
This block controls the slew rate of the internal reference
voltage when output voltage changes.
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6
DS3663BC-03 August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
