RT3614EE
Functional Block Diagram
IMONAVG
UVLO
GND
MUX
ADC
SVID Interface
Configuration Registers
Control Logic
PIN Function
Setting Code
Loop Control/
Protection Logic
DRVEN
VIN
ANS_EN
FLRAMP_PS0[1:0]
FLRAMP_PS1
Ring-back
Control
RGND
DAC
ERROR
PWM
CMP
AMP
VID
PWM1
PWM2
PWM3
PWM4
+
-
Offset
Cancellation
+
+
+
-
FB
TON
GEN/
Driver
ZCDx
VCBx
COMP
HFACLL_LIFT_PS1[1:0]
Interface
TONSET[3:0]
UDS[2:0]
ISEN1P
ISEN1N
+
-
Gm
IIMON1
+
-
RAMP
ICB1
IZD1
IOC1
Ai[1:0]
ISEN2P
ISEN2N
+
-
Gm
Gm
Gm
IIMON2
ICB2
IZD2
IOC2
VSEN
ISEN3P
ISEN3N
+
-
AQR_TH[2:0]
AQR/
IIMON3
ICB3
IZD3
IOC3
ANTIOVS
ANTIOVS_TH[2:0]
ZCDx
To TONGEN
IMON
Filter
IMONAVG
OVP/
UVP/
OCP
VSEN
IOCx
IMON
ISEN4P
ISEN4N
+
-
To Protection Logic
IIMON4
ICB4
Current
Balance
IZD4
IOC4
VCBx
ZCDx
ICBx
+
-
PER CSGM
0.6V/3.2V
Zero
Current
Detection
IZDx
ZCD_TH[1:0]
IMON VREF06
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS3614EE-01 December 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
