RT3606BC
Functional Block Diagram
UVLO
GND
MUX
ADC
MUX
ADC
SVID Interface
Configuration Registers
Control Logic
Loop Control Protection
Logic
IC1_M
IC2_M
IC3_M
IC4_M
IC1_A
DAC
Current Mirror
VID_M
VR address
H/L f ramp
DVID SR
Disable DVID compensation
Decrease GTV/SA ramp (only in 1-phase)
Zero load-liner
AI gain
VID_A
+
-
2V
IBIASI
IC2_A
IC3_A
OCS_M
OCS_A
PS_M PS_A
OV_X/NV_X/
DVIDTH_X
DVIDWIDTH_X
QR_X
QRWIDTH_X
OCS_TH_X
RSET_X
IBIAS
SW
OC_PER_X/OC_SUM_X
From Control Logic
DAC
DVID SR
DVIDTH_M
DVIDWIDTH_M
ICCMAX_X
OCP_PER_X
TONSET
PWM3
PSYS function
RGND
ERROR
AMP
Soft-Start & Slew Rate
Control
PWM
CMP
VSET_M
+
Offset
Cancellation
+
-
PWM1
PWM2
PVCC
FB
-
TON
GEN
+
PS_M
QRTH_M
QRWIDTH_M
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
COMP
Current Mirror
ISEN1P
ISEN1N
+
-
1/3
IC1_M
IB1_M
+
GM
-
V
REF
RSET_M
Current Mirror
Driver
ISEN2P
ISEN2N
+
-
Current Balance
IB1_M IB2_M IB3_M
IC2_M
IB2_M
IMONI_M
IMON Filter
Current Mirror
BOOTA1
UGATEA1
PHASEA1
LGATEA1
ISEN3P
ISEN3N
+
-
PWMA1
IC3_M
IB3_M
Anti-OVS
+
OCS_M
OCS_TH_M
-
Anti-OVS behavior
IMON
DVID SR
DVIDTH_A
DVIDWIDTH_A
From Control Logic
DAC
TONSETA
RGNDA
ERROR
AMP
Soft-Start & Slew Rate
Control
PWM
CMP
VSET_A
+
Offset
Cancellation
+
-
TON
GEN
FBA
-
+
PS_A
QRTH_A
COMPA
PWMA2
Current Mirror
ISENA1P
ISENA1N
QRWIDTH_A
+
-
1/3
IC1_A
IB1_A
+
GM
-
RSET_A
Current Mirror
Current Balance
ISENA2P
ISENA2N
+
-
IC2_A
IB2_A
IB1_A IB2_A
IMONI_A
IMON Filter
IMONA
+
OCS_A
OCS_TH_A
-
V
REFI
+
-
VREF
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS3606BC-07 August 2018
www.richtek.com
5
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