®
R2600
RISC DSP Communication
RDC
FAST ETHERNET RISC PROCESSOR
1. Features
- The data rates are programmable from 50 to
460.8K baud (max. to 1Mbps)
l CPU Core
- RDC’s proprietary RISC architecture
- Five-stage pipeline architecture
- Operation frequency: 100MHz
- Supports a 8K-byte uniform cache
- The character options are programmable for 1 start
bit; 1, 1.5 or 2 stop bits; even, odd or no parity, 5~8
data bits
l ROM/RAM/SDRAM
Addressing Space
Controller
and
l RDC Debug Tool Support
- RDC debug tool with a JTAG-like interface
- Supports 16-bit data bus width
- Flash ROM/SRAM control interface
- SDRAM control interface
- 16M addressing space
l
General Programmable I/O
- 48 programmable I/O ports mixed with other
functions
- 64K-byte I/O space
- 8 dedicated GPIOs for WLAN block
- Pins individually configurable to input or output
mode
l Two Independent DMA Controllers
- Supports high-speed DMA transfers
l
Two 10/100M Fast Ethernet MAC Ports
- IEEE 802.3u MII interface
l Interrupt Controller
- Provides 8 maskable external interrupt channels
- IEEE 802.3x flow control in full-duplex mode
- Internal loop-back self-test circuit support
- Descriptor architecture for packet TX/RX
l Counter/Timers
- Three independent programmable 16-bit timers
- One programmable watchdog timer which can
generate NMI or reset.
l
PCI Control Interface Support
- Supports up to 3 PCI masters
- Speed up to 33MHz
l High Performance UART Ports
- Supports 2 high performance UARTs with
send/receive 16-byte FIFOs
l
Two Card Bus Interface Support
- Programmable baud rate generator
- On-chip A/D and D/A Converters for I/Q data,
TSSI and AGCs.
l
IEEE 802.11b/g WLAN Support
- Security: 64/128 WEP, WPA, AES
- Advanced power saving algorithm for dynamic
network traffic environment
- Supports 6, 9, 12, 18, 24, 36, 48, 54 Mbps for OFDM;
5.5, 11Mbps for CCK; and 1,2 Mbps for barker
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page 2 of REV 1.0 Jul. 18 2005
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RDC [ RDC SEMICONDUCTOR ]
