®
R2022
RISC DSP Communication
RDC
FAST ETHERNET RISC PROCESSOR
2. Block Diagram
INT2
INT1
INT0
CLKOUTA
DRQ0
DRQ1
INT6-INT5
X2
Clock and
X1
Interrupt
Control Unit
Timer Control
Unit
DMA
Unit
VCC
GND
Power
Management
RST_n
MAC1
MII1
MII0
Cache
MCS_n
UCS_n
Instruction
Queue (64bits)
Chip
Select
Unit
MAC0
PCS5_n
PCS3_n
PCS2_n
PCS0_n
Instruction
Decoder
Micro
ROM
PIO
Unit
PIO[39:0]
Control Signal
Register
File
EA / LA
Address
DCD0_n
SIN0
DSR0_n
CTS0_n
RI0_n
General,
16550 UART
Serial
ARDY
Refresh
Control
Unit
Segment,
Eflag Register
Port0
RTS0_n
SOUT0
DTR0_n
DCD1_n
SIN1
DSR1_n
CTS1_n
RI1_n
RTS1_n
SOUT1
DTR1_n
SDRAM/Bus
Interface
Unit
16550 UART
Serial
ALU
(Special,
Logic,
Adder,
BSF)
SD_CLK
Execution
Unit
WE_n
CAS_n
RAS_n
BA[1:0]
Port1
A[21:0]
BHE_n
RD_n
D[15:0]
ALE
WR_n/BWSEL
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page 3 of REV 1.0 Sep. 20 2006
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RDC [ RDC SEMICONDUCTOR ]
