72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
Pin Descriptions
Symbol
Type
Function
CLK
Input
Input
Clock: All input signals (except G#) and output signals are referenced to the rising edge of CLK.
CKE#
Clock Enable: This active low input enables the internal clock signal. If CKE# is driven high, the chip
ignores the clock (all signals except G#) and suspends pending operations.
CE1#,
CE2,
CE3#
Input
Chip Enable Inputs: These inputs determine whether the RAM begins a read, write, or deselect
cycle. When qualified by LD# low, all three inputs must be true to select the chip and begin a read or
write cycle. When qualified by LD# low, at least one chip enable input must be false to begin a
deselect cycle.
LD#
Input
Load Input: This active low input loads the external address, and begins a new read or write cycle.
Once a read or write cycle is initiated, LD# must be negated to advance the internal burst counter.
LD# cannot be asserted for two consecutive clocks.
R/W#
Input
Input
Read/Write Input: When LD# is asserted and the chip is enabled, this input determines whether the
chip begins a read (R/W# high) or write (R/W# low) cycle.
BW [a:d]
#
Byte Write Inputs: These active low inputs allow write data to be written (BWx# low) or masked
(BWx# high) during write cycles. During read and deselect cycles, the BWx# inputs are ignored.
BWa# controls DQa, BWb# controls DQb, BWc# controls DQc, and BWd# controls DQd.
A, A1, A0
DQ [a:d]
G#
Input
Address Inputs: Used to select a starting burst address location. The address inputs are sampled
when LD# is low and the chip is enabled. Inputs A1 and A0 determine the starting address for all
burst cycles.
Input/
Output
Data I/O Inputs: These pins deliver output data during burst read cycles. Output data is valid tCO
from the rising edge of the clock. These data pins also allow input write data to be written to the
chip. Input data must satisfy setup and hold timing specifications.
Input
Input
Input
Output Enable Input: This active low input enables the output data buffers to drive output data
during read cycles. When negated, G# three states the data bus. The data output pins are
automatically three stated during write and deselect cycles.
LBO#
DNU
Linear Burst Order Input: This signal must remain in steady state.
Low – Linear burst.
High – Interleaved burst.
Do Not Use Input: These unused pins may be left open circuit, and should be reserved for future
address pins.
TCK
TMS
TDI
Input
Input
Test Clock: Input clock for boundary scan. If boundary scan is not used, TCK must be tied to VSS.
Test Mode Select: This input controls the TAP controller and is sampled on the rising edge of TCK.
Test Data In: This is the serial data input for boundary scan testing.
Test Data Out: This is the serial data output for boundary scan testing.
Core Power Supply: Connect to 3.3V or 2.5V.
Input
TDO
VDD
Output
Supply
Supply
Supply
-
VDDQ
VSS, VSSQ
NC
I/O Power Supply: Connect to 3.3V (only on VDD = 3.3V devices) or 2.5V.
Ground: VSS and VSSQ are connected inside the chip.
No Connect: - These pins do not connect to the chip.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
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Revision 1.0
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
