168-pin Enhanced SDRAM DIMM
8MB, 16MB, 32MB DIMM
Preliminary Data Sheet
Common Parameters
Symbol
Parameter
7.5
10
Units Notes
Min
2
Max
Min
2.5
1
Max
tCS
tCH
Command Setup Time
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Command Hold Time
1
-
-
tAS
Address and Bank Select Setup Time
Address and Bank Select Hold Time
RAS to CAS Delay
2
-
2.5
1
-
tAH
1
-
-
tRCD
tRC
tRAS
tRP
tRRD
tCCD
15
37.5
22.5
15
15
7.5
-
20
50
30
20
20
10
-
Bank Cycle Time
120,000
120,000
Active Command Period
Precharge Time
120,000
120,000
-
-
-
-
-
-
Bank to Bank Delay Time
CAS to CAS Delay Time (Same Bank)
Refresh Cycle
Symbol
Parameter
7.5
10
Units Notes
Min
Max
64
-
Min
Max
64
-
tREF
Refresh Period
-
-
ms
ns
1, 2
3
tSREX
Self Refresh Exit Time
2CLK+tRC
2CLK+tRC
Notes:
1. 4096 cycles.
2. Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.
3. Self-Refresh exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self-Refresh Exit is not
completed until tRC is satisfied once the Self-Refresh Exit command is registered.
Read Cycle
Symbol
Parameter
7.5
10
Units Notes
Min
3
Max
Min
3
Max
tOH2
tOH1
tLZ
Data Out Hold Time CL = 2,3
Data Out Hold Time CL = 1
-
-
-
-
ns
ns
ns
2
2
Data Out to Low Impedance
0
-
0
-
tHZ2
tHZ1
tDQZ
Data Out to High Impedance CL = 2, 3
Data Out to High Impedance CL = 1
DQM Data Out Disable Latency
-
7.5
4.5
-
-
8
5
-
ns
ns
1
1
-
-
2
2
CLK
Notes:
1. Referenced to the time at which the output achieves an open circuit condition, not to output voltage levels.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 8 of 13
Revision 3.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
