16MB ESDRAM SO-DIMM
Serial Presence Detect Operation
This module incorporates Serial Presence Detect (SPD). The SPD function is implemented using a 2048 bit EEPROM.
This nonvolatile storage device contains 256 bytes. The first 128 bytes is programmed by Enhanced to identify the module
type and organization, component speed, and other attributes relevant to the system controller. The remaining 128 bytes of
storage are available for use by the customer. System Read/Write operations between the master (system logic) and the
slave EEPROM device (SO-DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data signals).
Pin Description
Symbol
Type
Function
/RAS, /CAS,
/WE
Input
Command Inputs: Sampled on the rising edge of CLK, these inputs define the command
to be executed.
CK0, CK1
CKE0
/S0
Input
Input
Input
Clock: All ESDRAM input signals are sampled on the positive edge of CK0 and CK1.
CK0 is wired to U1,U2,U5,U6, and CK1 is wired to U3,U4,U7,U8.
Clock Enable: Activates the CK0 signal when high and deactivates CK0 internally. CKE0
low initiates the Power Down, Suspend, and Self-Refresh modes.
Chip Select: Active low /S0 enables the command decoder and disables the command
decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
DQMB7-
DQMB0
Input
Input
Input
Data I/O Mask Inputs: DQM inputs mask write data (zero latency) and acts as a
synchronous output enable (2 cycle latency) for read data.
BA0
Bank Address: This input defines to which of the 2 banks a given command is being
applied. This address input is also used to program the Mode Register.
A10-A0
Address Inputs: A10-A0 defines the row address for the Bank Activate command. A8-A0
define the column address for Read and Write commands. A10/AP invokes the Auto-
Precharge operation. During manual Precharge commands, A10/AP low specifies a
single bank precharge while A10/AP high precharges all banks. The address inputs are
also used to program the Mode Register.
DQ63-DQ0
Input/
Output
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these
pins and must be set-up and held relative to the rising edge of clock. For Read cycles,
the device drives output data on these pins after the CAS latency is satisfied.
VDD
VSS
Supply
Supply
Power supply (+3.3V)
Ground
SDA
Input/
Output
Serial Presence Detect Data: SDA is a bidirectional pin used to transfer addresses, data
into, and data out of the EEPROM.
SCL
Input
Clock for Serial Presence Detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
NC
-
-
No connect.
RSVD
Reserved for future use.
Rev. 1.1
3
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
