168-pin Enhanced SDRAM DIMM
8MB, 16MB, 32MB DIMM
Preliminary Data Sheet
Write Cycle
Symbol
Parameter
7.5
10
Units Notes
Min
2
Max
Min
2.5
1
Max
tOS
tOH
Data In Setup Time
Data In Hold Time
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
1
tDPL
tDAL
tDQW
Data Input to Precharge
Data In to Active/Refresh
DQM Write Mask Latency
7.5
24
0
10
30
0
ns
1
CLK
Notes:
1. tDAL must satisfy tDPL + tRP.
Clock Frequency and Latency
Symbol
Parameter
Speed Sort
Units Notes
7.5
10
fCK
tCK
Clock Frequency
133
7.5
2
66
15
1
100
10
2
50
20
1
MHz
ns
Clock Cycle Time
tAA
CAS Latency
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tRCD
tRL
RAS to CAS Delay
RAS Latency
2
1
2
1
4
2
4
2
tRC
Bank Cycle Time
5
3
5
3
tRAS
tRP
Minimum Bank Active Time
Precharge Time
3
2
3
2
2
1
2
1
tDPL
tDAL
tRRD
tCCD
tWL
Data In to Precharge
Data In to Active/Refresh
Bank to Bank Delay Time
CAS to CAS Delay Time
Write Latency
1
1
1
1
3
2
3
2
2
1
2
1
1
1
1
1
0
0
0
0
tDQW
tDQZ
tCSL
DQM Write Mask Latency
DQM Data Disable Latency
Clock Suspend Latency
0
0
0
0
2
2
2
2
1
1
1
1
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 3.1
Page 9 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
