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FM4005 参数 Datasheet PDF下载

FM4005图片预览
型号: FM4005
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器伴侣 [Integrated Processor Companion]
分类和应用:
文件页数/大小: 23 页 / 236 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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FM4005  
Counter 2 Polarity is C2P, bit 1; the Cascade Control  
is CC, bit 2; and the Read Counter bit is RC bit 3.  
registers. The registers are frozen and will not be  
updated again until the R bit is cleared to 0. R is used  
for reading the time.  
C1P  
16-bit Counter  
Setting the W bit to 1 locks the user registers.  
Clearing it to 0 causes the values in the user registers  
to be loaded into the timekeeper core. W is used for  
writing new time values. Users should be certain not  
to load invalid values, such as FFh, to the  
timekeeping registers. Updates to the timekeeping  
core occur continuously except when locked.  
CNT1  
C2P  
CNT2  
16-bit Counter  
CC  
Backup Power  
The real-time clock/calendar is intended to be  
permanently powered. When the primary system  
power fails, the voltage on the VDD pin will drop.  
When VDD drops below 2.5V, the RTC (and event  
counters) will switch to the backup power supply on  
VBAK. The clock uses very little current which  
maximizes battery or capacitor life.  
Figure 6. Event Counter  
The polarity bits must be set prior to setting the  
counter value(s). If a polarity bit is changed, the  
counter may inadvertently increment. If the counter  
pins are not being used, tie them to ground.  
When inserting a battery into a system board,  
higher-than-normal battery drain may occur. It is  
recommended that your system power-up  
procedure complies with one of the following:  
Serial Number  
A memory location to write a 64-bit serial number is  
provided. It is a writeable nonvolatile register that  
can be locked by the user once the serial number is  
set. The serial number registers can be written an  
unlimited number of times. However once the lock bit  
is set the values cannot be altered and the lock  
cannot be removed. Once locked the serial number  
registers can still be read by the system.  
Scenario #1  
a) Apply Vdd to board.  
b) Insert battery. At this point, IBAK is zero.  
c) When VDD is powered down, the IBAK current  
will be less than 1µA.  
The serial number is located in registers 11h to 18h.  
The lock bit is SNL, register 0Bh, bit 7. Setting the  
SNL bit to a 1 disables writes to the serial number  
registers, and the SNL bit cannot be cleared.  
Scenario #2  
a) Insert battery without power to board (VDD is  
off). At this point, the IBAK current may be  
much higher than the 1µA spec limit. An  
extended period of time (days) in this state  
could significantly reduce battery life.  
b) Apply VDD to board. IBAK goes to zero.  
c) When VDD is powered down, the IBAK current  
will be less than 1µA.  
Real-time Clock Operation  
The real-time clock (RTC) is a timekeeping device  
that can be battery or capacitor backed for  
permanently-powered operation. It offers a software  
calibration feature that allows high accuracy.  
Trickle Charger  
The RTC consists of an oscillator, clock divider, and  
a register system for user access. It divides down the  
32.768 kHz time-base and provides a minimum  
resolution of seconds (1Hz). Static registers provide  
the user with read/write access to the time values. It  
includes registers for seconds, minutes, hours, day-  
of-the-week, date, months, and years. A block  
diagram (Figure 7) illustrates the RTC function.  
To facilitate capacitor backup the VBAK pin can  
optionally provide a trickle charge current. When the  
VBC bit, register 0Bh bit 2, is set to 1 the VBAK pin  
will source approximately 15 µA until VBAK  
reaches VDD or 3.75V whichever is less. In 3V  
systems, this charges the capacitor to VDD without  
an external diode and resistor charger. In 5V systems,  
it provides the same convenience and also prevents  
the user from exceeding the VBAK maximum  
voltage specification.  
The user registers are synchronized with the  
timekeeper core using R and W bits in register 00h  
described below. Changing the R bit from 0 to 1  
transfers timekeeping information from the core into  
holding registers that can be read by the user. If a  
timekeeper update is pending while R is set, then the  
core will be updated prior to loading the user  
! Note: systems using lithium batteries should clear  
the VBC bit to 0 to prevent battery charging. The  
VBAK circuitry includes an internal 1 Kseries  
resistor as a safety element.  
Rev. 2.3  
Oct. 2006  
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