FM33256/FM3316 SPI Companion w/ FRAM
60 ms increments via a 5-bit nonvolatile setting
(register 0Ch).
active if the watchdog reaches the timeout without
being restarted. If a reset occurs, the timer will restart
on the rising edge of the reset pulse. If WDE is not
enabled, the watchdog timer still runs but has no
effect on /RST. The second control is a nibble that
restarts the timer, thus preventing a reset. The timer
should be restarted after changing the timeout value.
= 1010b
to restart
WR3-0
100 ms
clock
Timebase
Down Counter
/RST
Watchdog
Timer Settings
This procedure must be followed to properly load the
watchdog registers:
Address
WDE
Figure 3. Watchdog Timer
1. Write the StartTime value
2. Write the EndTime value and WDE=1 0Ch
3. Issue a Restart command 0Ah
0Bh
The watchdog also incorporates a window timer
feature that allows a delayed start. The starting time
and ending time defines the window and each may be
set independently. The starting time has 25 ms
resolution and 0 ms to 775 ms range.
The restart command in step 3 must be issued before
DOG2, which was programmed in step 2. The window
t
timer starts counting when the restart command is
issued.
Watchdog
Restart
Start
Time
End
Time
Manual Reset
The /RST is a bi-directional signal allowing the
FM33xx to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms (max.). This effectively filters and de-
bounces a reset switch. After this timeout (tRPW), the
user may continue pulling down on the /RST pin, but
SPI commands will not be locked out.
Window
RST
100 ms (max)
Figure 4. Window Timer
The watchdog EndTime value is located in register
0Ch, bits 4-0, the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 0Ah. Writing the correct
pattern will also cause the timer to load new timeout
values. Writing other patterns to this address will not
affect its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
timer as described above. This assures that the full
timeout is provided immediately after enabling. The
watchdog is disabled when VDD drops below VTP.
Note setting the EndTime timeout setting to all
zeroes (00000b) disables the timer to save power.
The listing below summarizes the watchdog bits.
MCU
RST
FM33xx
Reset
Switch
Switch
Behavior
FM33xx
drives
RST
100 ms (max.)
Figure 5. Manual Reset
Note the internal weak pull-up eliminates the need
for additional external components.
Watchdog StartTime WDST4-0 0Bh, bits 4-0
Watchdog EndTime WDET4-0 0Ch, bits 4-0
Reset Flags
Watchdog Enable
Watchdog Restart
Watchdog Flags
WDE
0Ch, bit 7
0Ah, bits 3-0
09h, bit 7
In case of a reset condition, a flag bit will be set to
indicate the source of the reset. A low-VDD reset is
indicated by the POR bit, register 09h bit 5. There are
two watchdog reset flags - one for an early fault
(EWDF) and the other for a late fault (LWDF),
located in register 09h bits 7 and 6. A manual reset
will result in no flag being set, so the absence of a
flag is a manual reset. Note that the bits are set in
response to reset sources but they must be cleared by
the user. It is possible to read the register and have
WR3-0
EWDF,
LWDF
09h, bit 6
The programmed StartTime value is a guaranteed
maximum time while the EndTime value is a
guaranteed minimum time, and both vary with
temperature and VDD voltage. The watchdog has two
additional controls associated with its operation. The
nonvolatile enable bit WDE allows the /RST to go
Rev. 1.0
Dec. 2006
Page 5 of 28
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
