FM3104/16/64/256
to be loaded into the timekeeper core. W is used for
writing new time values. Users should be certain not
to load invalid values, such as FFh, to the
timekeeping registers. Updates to the timekeeping
core occur continuously except when locked.
the same convenience and also prevents the user from
exceeding the VBAK maximum voltage specification.
In the case where no battery is used, the VBAK pin
should be tied according to the following conditions:
Backup Power
•
•
For 3.3V systems, VBAK should be tied to VDD
This assumes VDD does not exceed 3.75V.
.
The real-time clock/calendar is intended to be
permanently powered. When the primary system
power fails, the voltage on the VDD pin will drop.
When VDD is less 2.5V the RTC (and event counters)
will switch to the backup power supply on VBAK. The
clock operates at extremely low current in order to
maximize battery or capacitor life. However, an
advantage of combining a clock function with FRAM
memory is that data is not lost regardless of the
backup power source.
For 5V systems, attach a 1 µF capacitor to VBAK
and turn the trickle charger on. The VBAK pin
will charge to the internal backup voltage which
regulates itself to about 3.6V. VBAK should not
be tied to 5V since the VBAK (max) specification
will be exceeded. A 1 µF capacitor will keep
the companion functions working for about 1.5
second.
Although VBAK may be connected to VSS, this is not
recommended if the companion is used. None of the
companion functions will operate below about 2.5V.
Trickle Charger
To facilitate capacitor backup the VBAK pin can
optionally provide a trickle charge current. When the
VBC bit, register 0Bh bit 2, is set to 1 the VBAK pin
will source approximately 15 µA until VBAK reaches
VDD or 3.75V whichever is less. In 3V systems, this
charges the capacitor to VDD without an external
diode and resistor charger. In 5V systems, it provides
, Note: systems using lithium batteries should clear
the VBC bit to 0 to prevent battery charging. The
VBAK circuitry includes an internal 1 KΩ series
resistor as a safety element.
512 Hz
1 Hz
/OSCEN
W
32.768 kHz
crystal
Clock
Update
Logic
Divider
Date
Years
8 bits
Months
5 bits
CF
6 bits
Hours
6 bits
Minutes
7 bits
Seconds
7 bits
Days
3 bits
R
User Interface Registers
Figure 7. Real-Time Clock Core Block Diagram
error in ppm and writes the appropriate correction
value to the calibration register. The correction
factors are listed in the table below. Positive ppm
errors require a negative adjustment that removes
pulses. Negative ppm errors require a positive
correction that adds pulses. Positive ppm adjustments
have the CALS (sign) bit set to 1, where as negative
ppm adjustments have CALS = 0. After calibration,
the clock will have a maximum error of 2.17 ppm
Calibration
When the CAL bit in a register 00h is set to 1, the
clock enters calibration mode. In calibration mode,
the CAL/PFO output pin is dedicated to the
calibration function and the power fail output is
temporarily unavailable. Calibration operates by
applying a digital correction to the counter based on
the frequency error. In this mode, the CAL/PFO pin
is driven with a 512 Hz (nominal) square wave. Any
measured deviation from 512 Hz translates into a
timekeeping error. The user converts the measured
or
0.09 minutes per month at the calibrated
temperature.
Rev. 3.2
July 2010
Page 7 of 25
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
