FM3130 Integrated RTC/Alarm with 64Kb FRAM
VBC bit (register 0Eh, bit 2) is set to a „1‟, the VBAK
pin will source approximately 80 µA until VBAK
reaches VDD. This charges the capacitor to VDD
without an external diode and resistor charger.
There is a Fast Charge mode which is enabled by the
FC bit (register 0Eh, bit 1). In this mode the trickle
charger current is set to approximately 1 mA,
allowing a large backup capacitor to charge more
quickly.
In the case where no battery is used, the VBAK
pin should be tied to VSS.
Note: systems using lithium batteries should clear
the VBC bit to 0 to prevent battery charging. The
VBAK circuitry includes an internal 1 K series
resistor as a safety element. The trickle charger is UL
Recognized.
512 Hz or
SW out
/OSCEN
Oscillator
W
32.768 kHz
crystal
Clock
Divider
Update
Logic
1 Hz
E
Date
6 bits
Years
8 bits
Months
5 bits
CF
Hours
6 bits
Minutes
Seconds
7 bits
7 bits
T
Days
3 bits
t
n
e
E
R
User Interface Registers
m
4
L
R
e
Figure 2. Real-Time Clock Core Block Diagram
6
c
1
a
with bits CAL.4-0lin register 01h. This value only
Calibration
3
can be written when the CAL bit is set to a „1‟. To
p
O
When the CAL bit in register 00h is set to „1‟, the
clock enters calibration mode. In calibration mode,
the ACS output pin is dedicated to the calibration
exit the calibration mode, the user must clear the
e
M
CAL bit to a „0‟. When the CAL bit is „0‟, the ACS
F
pin will revert to another function as defined in
Table 3. Control Bit Settings for ACS Pin.
function and the power fail output is temporarily
S
:
t
unavailable. Calibration operates by applying a
e
c
digital correction to the counter based on the
frequency error. In this mode, the ACS pin is driven
v
e Crystal Type
i
B
with a 512 Hz (nominal) square wave. Any measured r
t
i
The crystal oscillator is designed to use a 12.5pF
a
deviation from 512 Hz translates into a timekeeping
error. The user converts the measured error in ppm
and writes the appropriate correction value to the
crystal without the need for external components,
D
snuch as loading capacitors. The FM3130 device has
r
built-in loading capacitors that match the crystal.
o
O
calibration register. The correction factors are listed
e
in the table below. Positive ppm errors require a t
N
l
If a 32.768kHz crystal is not used, an external
oscillator may be connected to the FM3130. Apply
the oscillator to the X1 pin. Its high and low voltage
levels can be driven rail-to-rail or amplitudes as low
as approximately 500mV p-p. To ensure proper
operation, a DC bias must be applied to the X2 pin.
It should be centered between the high and low levels
on the X1 pin. This can be accomplished with a
voltage divider. See Figure 3.
negative adjustment that removes pulses. Negative
ppm errors require a positive correction that Aadds
pulses. Positive ppm adjustments have the CALS
(sign) bit set to „1‟, whereas negative ppm
adjustments have CALS = 0. After calibration, the
clock will have a maximum error of 2.17 ppm or
0.09 minutes per month at the calibrated
temperature.
The calibration setting is battery-backed and must be
reloaded should the backup source fail. It is accessed
Rev. 3.2
Sept. 2011
Page 4 of 22
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
