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FM28V100_10 参数 Datasheet PDF下载

FM28V100_10图片预览
型号: FM28V100_10
PDF下载: 下载PDF文件 查看货源
内容描述: 为1Mbit字节宽度的F- RAM存储器 [1Mbit Bytewide F-RAM Memory]
分类和应用: 存储
文件页数/大小: 13 页 / 315 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号FM28V100_10的Datasheet PDF文件第4页浏览型号FM28V100_10的Datasheet PDF文件第5页浏览型号FM28V100_10的Datasheet PDF文件第6页浏览型号FM28V100_10的Datasheet PDF文件第7页浏览型号FM28V100_10的Datasheet PDF文件第9页浏览型号FM28V100_10的Datasheet PDF文件第10页浏览型号FM28V100_10的Datasheet PDF文件第11页浏览型号FM28V100_10的Datasheet PDF文件第12页  
FM28V100 - 128Kx8 FRAM  
Read Cycle AC Parameters (TA = -40° C to +85° C, CL = 30 pF, unless otherwise specified)  
VDD 2.0 to 2.7V  
VDD 2.7 to 3.6V  
Symbol Parameter  
Min  
105  
-
Max  
Min  
90  
-
Max  
-
Units Notes  
tRC  
tCE  
Read Cycle Time  
-
70  
105  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable Access Time  
60  
90  
-
tAA  
tOH  
tAAP  
tOHP  
tCA  
tPC  
Address Access Time  
-
-
Output Hold Time  
20  
-
20  
-
Page Mode Address Access Time  
Page Mode Output Hold Time  
Chip Enable Active Time  
40  
-
30  
-
3
3
70  
35  
0
-
60  
30  
0
-
Precharge Time  
-
-
tAS  
Address Setup Time (to /CE1, CE2 active)  
Address Hold Time (/CE-controlled)  
Output Enable Access Time  
Chip Enable to Output High-Z  
Output Enable High to Output High-Z  
-
-
tAH  
tOE  
tHZ  
tOHZ  
70  
-
-
-
60  
-
-
-
25  
10  
10  
15  
10  
10  
ns  
ns  
1
1
-
-
Write Cycle AC Parameters (TA = -40° C to +85° C, unless otherwise specified)  
VDD 2.0 to 2.7V  
VDD 2.7 to 3.6V  
Symbol Parameter  
Min  
105  
70  
70  
35  
40  
22  
0
Max  
Min  
90  
60  
60  
30  
30  
18  
0
Max  
Units Notes  
tWC  
tCA  
Write Cycle Time  
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable Active Time  
tCW  
tPC  
Chip Enable to Write Enable High  
Precharge Time  
-
-
-
-
tPWC  
Page Mode Write Enable Cycle Time  
Write Enable Pulse Width  
-
-
tWP  
-
-
tAS  
Address Setup Time (to /CE1, CE2 active)  
Address Hold Time (/CE-controlled)  
Page Mode Address Setup Time (to /WE low)  
Page Mode Address Hold Time (to /WE low)  
Write Enable Low to Chip Disabled  
Write Enable Low to A(16:3) Change  
A(16:3) Change to Write Enable High  
Data Input Setup Time  
-
-
tAH  
70  
8
-
60  
5
-
tASP  
tAHP  
tWLC  
tWLA  
tAWH  
tDS  
-
-
20  
30  
30  
105  
20  
0
-
15  
25  
25  
90  
15  
0
-
-
-
-
-
-
-
-
-
tDH  
Data Input Hold Time  
-
-
tWZ  
Write Enable Low to Output High Z  
Write Enable High to Output Driven  
Write Enable to CE-Active Setup Time  
Write Enable to CE-Inactive Hold Time  
-
10  
-
-
10  
-
ns  
ns  
ns  
ns  
1
tWX  
tWS  
5
5
1
0
-
-
0
-
1,2  
1,2  
tWH  
Notes  
0
0
-
1
2
This parameter is characterized but not 100% tested.  
The relationship between CE’s and /WE determines if a /CE- or /WE-controlled write occurs.  
Power Cycle Timing (TA = -40° C to +85° C, VDD = 2.0V to 3.6V unless otherwise specified)  
Symbol  
tVR  
Parameter  
Min  
50  
100  
250  
0
Max  
Units  
Notes  
1
1
VDD Rise Time  
-
-
-
-
µs/V  
µs/V  
µs  
tVF  
VDD Fall Time  
tPU  
tPD  
Notes  
Power Up (VDD min) to First Access Time  
Last Access to Power Down (VDD min)  
µs  
1
Slope measured at any point on VDD waveform.  
Rev. 1.2  
May 2010  
Page 8 of 13