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FM25VN02-G 参数 Datasheet PDF下载

FM25VN02-G图片预览
型号: FM25VN02-G
PDF下载: 下载PDF文件 查看货源
内容描述: 256Kb的3V串行F-RAM存储器 [256Kb Serial 3V F-RAM Memory]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 17 页 / 338 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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FM25V02 - 256Kb SPI FRAM  
W
S
Instruction Decode  
Clock Generator  
Control Logic  
HOLD  
C
Write Protect  
4096 x 64  
FRAM Array  
Instruction Register  
15  
8
Address Register  
Counter  
Q
D
Data I/O Register  
3
Nonvolatile Status  
Register  
Figure 1. Block Diagram  
Pin Descriptions  
Pin Name  
I/O  
Description  
/S  
Input  
Chip Select: This active-low input activates the device. When high, the device enters  
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When  
low, the device internally activates the C signal. A falling edge on /S must occur prior  
to every op-code.  
C
Input  
Input  
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on  
the rising edge and outputs occur on the falling edge. Since the device is static, the  
clock frequency may be any value between 0 and 40 MHz and may be interrupted at  
any time.  
/HOLD  
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation  
for another task. When /HOLD is low, the current operation is suspended. The device  
ignores any transition on C or /S. All transitions on /HOLD must occur while C is low.  
This pin has a weak internal pull-up (see RIN spec, pg 11). However, if it is not used,  
the /HOLD pin should be tied to VDD  
.
/W  
D
Input  
Input  
Write Protect: This active-low pin prevents write operations to the Status Register  
only. A complete explanation of write protection is provided on pages 6 and 7. If not  
used, the /W pin should be tied to VDD  
.
Serial Input: All data is input to the device on this pin. The pin is sampled on the  
rising edge of C and is ignored at other times. It should always be driven to a valid  
logic level to meet IDD specifications.  
* D may be connected to Q for a single pin data interface.  
Serial Output: This is the data output pin. It is driven during a read and remains tri-  
stated at all other times including when /HOLD is low. Data transitions are driven on  
the falling edge of the serial clock.  
Q
Output  
* Q may be connected to D for a single pin data interface.  
Power Supply  
Ground  
VDD  
VSS  
Supply  
Supply  
Rev. 2.0  
May 2010  
Page 2 of 17