FM25L04B - 4Kb 3V SPI F-RAM
WREN - Set Write Enable Latch
Data Transfer
All data transfers to and from the FM25L04B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
The FM25L04B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Command Structure
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 5 below illustrates the
WREN command bus configuration.
There are six commands called op-codes that can be
issued by the bus master to the FM25L04B. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Table 1. Op-code Commands
Name
Description
Op-code
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 A011b
0000 A010b
Set Write Enable Latch
Write Disable
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
WREN
WRDI
RDSR
WRSR
READ
WRITE
CS
0
1
2
3
4
5
1
6
1
7
0
SCK
SI
0
0
0
0
0
Hi-Z
SO
Figure 5. WREN Bus Configuration
CS
0
1
2
3
4
5
1
6
0
7
0
SCK
0
0
0
0
0
SI
Hi-Z
SO
Figure 6. WRDI Bus Configuration
Rev. 1.3
Feb. 2011
Page 5 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
