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FM25L256B-GTR 参数 Datasheet PDF下载

FM25L256B-GTR图片预览
型号: FM25L256B-GTR
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Circuit, 32KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8]
分类和应用: 存储
文件页数/大小: 14 页 / 148 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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FM25L256 Extended Temp.  
WP  
CS  
Instruction Decode  
Clock Generator  
Control Logic  
HOLD  
SCK  
Write Protect  
8192 x 32  
FRAM Array  
Instruction Register  
15  
8
Address Register  
Counter  
SI  
SO  
Data I/O Register  
3
D
E
Nonvolatile Status  
Register  
D
Figure 1. Block Diagram  
S
N
ME  
N
Pin Descriptions  
G
Pin Name  
/CS  
I/O  
Input  
Description  
I
Chip Select: This active low input activates the device. When high, the device enters  
low-power standby mode, ignores other inputs, and all outputs are tri-stBated. When  
S
6
low, the device internally activMates the SCK signal. A falling edge on /CS must occur  
5
prior to every op-code.  
Serial Clock: All I/O ac  
E
tivity is synchronized to the serial clock.2Inputs are latched on  
SCK  
Input  
Input  
O
the rising edge and outputs occur on the falling edge. SinceLthe device is static, the  
D
clock frequency may be any value between 0 and 20 MH5z and may be interrupted at  
C
2
any time.  
Hold: TheE/HOLD pin is used when the host CPU must interrupt a memory operation  
M
/HOLD  
W
F
for another task. When /HOLD is low, the current operation is suspended. The device  
R
:
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while  
E
e
SCK is low.  
v
/WP  
SI  
Input  
Input  
Write Protect: This active low pin prevents write operations to the status register only.  
i
T
N
A complete explanation of write ptrotection is provided on pages 6 and 7.  
Serial Input: All data is inpuat to the device on this pin. The pin is sampled on the  
O
n
rising edge of SCK and is ignored at other times. It should always be driven to a valid  
r
R
logic level to meet IDD specifications.  
e
N
t
l
* SI may be connected to SO for a single pin data interface.  
O
SO  
Output  
Serial Output: This is the data output pin. It is driven during a read and remains tri-  
stated at all other times including when /HOLD is low. Data transitions are driven on  
A
F
the falling edge of the serial clock.  
* SO may be connected to SI for a single pin data interface.  
Power Supply (3.0V to 3.6V)  
VDD  
VSS  
Supply  
Supply  
Ground  
Rev. 2.3  
March 2007  
Page 2 of 14