FM25L16
Data Transfer
WREN - Set Write Enable Latch
All data transfers to and from the FM25L16 occur in
8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
The FM25L16 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Command Structure
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect. Completing any write
operation will automatically clear the write-enable
latch and prevent further writes without another
WREN command. Figure 5 below illustrates the
WREN command bus configuration.
There are six commands called op-codes that can be
issued by the bus master to the FM25L16. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by an address and one
or more bytes of data.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Table 1. Op-code Commands
Name
Description
Op-code
00000110b
00000100b
00000101b
00000001b
00000011b
00000010b
Set Write Enable Latch
Write Disable
WREN
WRDI
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
Figure 5. WREN Bus Configuration
Figure 6. WRDI Bus Configuration
Rev. 3.0
Aug. 2006
Page 5 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
