FM25040B - 4Kb 5V SPI F-RAM
WRSR – Write Status Register
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status Register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25040B will return one byte with the
contents of the Status Register. The Status Register is
described in detail in the Status Register & Write
Protection section.
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive. Note
that on the FM25040B, /WP prevents writing to the
Status Register and the memory array. Prior to
sending the WRSR command, the user must send a
WREN command to enable writes. Note that
executing a WRSR command is a write operation and
therefore clears the Write Enable Latch. The bus
timing for RDSR and WRSR are shown below.
Figure 7. RDSR Bus Timing
Figure 8. WRSR Bus Timing
whether a write cycle is complete or not. The BP1 and
Status Register & Write Protection
BP0 bits control write protection features. They are
nonvolatile (shaded yellow). The WEL flag indicates
the state of the Write Enable Latch. This bit is
internally set by the WREN command and is cleared
by terminating a write cycle (/CS high) or by using
the WRDI command.
The write protection features of the FM25040B are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes
are enabled using WREN, writes to memory are
controlled by the /WP pin and the Status Register.
When /WP is low, the entire part is write-protected.
When /WP is high, the memory protection is subject
to the Status register. Writes to the Status Register
are performed using the WREN and WRSR
commands and subject to the /WP pin. The Status
Register is organized as follows.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write-
protected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0
Protected Address Range
None
180h to 1FFh (upper ¼)
100h to 1FFH (upper ½)
000h to 1FFh (all)
Table 2. Status Register
0
0
1
1
0
1
0
1
Bit
7
0
6
0
5
0
4
0
3
BP1
2
BP0
1
0
0
Name
WEL
Bits 0 and 4-7 are fixed at 0 and cannot be modified.
Note that bit 0 (/RDY in EEPROMs) is wired low
since F-RAM writes have no delay and the memory
is never busy. All EEPROMs use Ready to indicate
Rev. 1.2
Feb. 2011
Page 6 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
