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FM24CL64-GTR 参数 Datasheet PDF下载

FM24CL64-GTR图片预览
型号: FM24CL64-GTR
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Circuit, 8KX8, CMOS, PDSO8, GREEN, MS-012AA, SOIC-8]
分类和应用: 存储
文件页数/大小: 13 页 / 115 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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FM24CL64  
Electrical Specifications  
Absolute Maximum Ratings  
Symbol  
Description  
Ratings  
VDD  
VIN  
Power Supply Voltage with respect to VSS  
Voltage on any pin with respect to VSS  
-1.0V to +5.0V  
-1.0V to +5.0V  
and VIN < VDD+1.0V *  
TSTG  
TLEAD  
VESD  
Storage Temperature  
Lead Temperature (Soldering, 10 seconds)  
Electrostatic Discharge Voltage  
-55°C to +125°C  
300° C  
- Human Body Model (JEDEC Std JESD22-A114-B)  
- Machine Model (JEDEC Std JESD22-A115-A)  
Package Moisture Sensitivity Level  
4kV  
300V  
MSL-1  
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating  
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this  
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.  
DC Operating Conditions (TA = -40° C to + 85° C, VDD =2.7V to 3.65V unless otherwise specified)  
Symbol  
VDD  
Parameter  
Main Power Supply  
Min  
2.7  
Typ  
Max  
3.65  
Units  
V
Notes  
IDD  
VDD Supply Current  
@ SCL = 100 kHz  
@ SCL = 400 kHz  
@ SCL = 1 MHz  
1
75  
150  
400  
µA  
µA  
µA  
µA  
µA  
µA  
V
ISB  
ILI  
ILO  
VIL  
VIH  
VOL  
Standby Current  
Input Leakage Current  
Output Leakage Current  
Input Low Voltage  
Input High Voltage  
1
±1  
±1  
2
3
3
-0.3  
0.7 VDD  
0.3 VDD  
VDD + 0.5  
0.4  
V
V
Output Low Voltage  
@ IOL = 3.0 mA  
RIN  
Address Input Resistance (WP, A2-A0)  
For VIN = VIL (max)  
50  
1
5
4
KΩ  
MΩ  
V
For VIN = VIH (min)  
VHYS  
Input Hysteresis  
0.05 VDD  
Notes  
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.  
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.  
3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.  
4. This parameter is characterized but not tested.  
5. The input pull-down circuit is strong (50K) when the input voltage is below VIL and weak (1M) when the  
input voltage is above VIH.  
Rev. 3.1  
Mar. 2005  
Page 8 of 13