FM24CL64B
Stop
Start
S
Address & Data
Address MSB
By Master
Slave Address
0
A
A
Address LSB
A
Data Byte
A
P
By FM24CL64
Acknowledge
Figure 5. Single Byte Write
Start
Stop
P
Address & Data
Address MSB
By Master
S
Slave Address
0
A
A
Address LSB
A
Data Byte
A
Data Byte
A
By FM24CL64
Acknowledge
Figure 6. Multiple Byte Write
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24CL64B uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
most likely create
a bus contention as the
FM24CL64B attempts to read out additional data
onto the bus. The four valid methods are:
1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.
Current Address & Sequential Read
2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a stop in the 9th clock
cycle.
As mentioned above the FM24CL64B uses an
internal latch to supply the address for a read
operation. A current address read uses the existing
value in the address latch as a starting place for the
read operation. The system reads from the address
immediately following that of the last operation.
4. The bus master issues a start in the 9th clock
cycle.
If the internal address reaches 1FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 below show the proper operation for current
address reads.
To perform a current address read, the bus master
supplies a device address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the
FM24CL64B will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
To perform a selective read, the bus master sends out
the device address with the LSB set to 0. This
specifies a write operation. According to the write
protocol, the bus master then sends the address bytes
that are loaded into the internal address latch. After
the FM24CL64B acknowledges the address, the bus
Each time the bus master acknowledges a byte,
this indicates that the FM24CL64B should read
out the next sequential byte.
Rev. 3.0
Jan. 2012
Page 6 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
