FM24CL16
Overview
Two-wire Interface
The FM24CL16 is a serial FRAM memory. The
memory array is logically organized as a 2,048 x 8
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24CL16 and a serial
EEPROM with the same pinout relates to its superior
write performance.
The FM24CL16 employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24CL16 in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24CL16 is always a slave device.
Memory Architecture
When accessing the FM24CL16, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The 2,048 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish from other non-memory
devices), a row address, and a segment address. The
row address consists of 8-bits that specify one of 256
rows. The 3-bit segment address specifies one of 8
segments within each row. The complete 11-bit
address specifies each byte uniquely.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that define
the four states. Detailed timing diagrams are in the
electrical specifications.
Most functions of the FM24CL16 either are
controlled by the two-wire interface or handled
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation is complete.
This is explained in more detail in the interface
section below.
VDD
Rmin = 1.1 K
Ω
Rmax = tR/Cbus
Microcontroller
SDA SCL
FM24CL16
SDA SCL
Other Slave
Device
Note that the FM24CL16 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to ensure
that VDD is within data sheet tolerances to prevent
incorrect operation.
Figure 2. Typical System Configuration
Rev 3.3
Nov. 2005
Page 3 of 13
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
