FM24C256
Address
Latch
4,096 x 64
FRAM Array
Counter
8
`
SDA
Serial to Parallel
Converter
Data Latch
SCL
WP
Control Logic
A0-A2
Figure 1. Block Diagram
Pin Description
Pin Name
Type
Pin Description
A0-A2
Input
Address 2-0: These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
WP
Input
I/O
Write Protect: When WP is high, the entire array will be write-protected. When WP is
low, all addresses may be written. This pin is internally pulled down.
SDA
Serial Data/Address: This is a bi-directional input used to shift serial data and
addresses for the two-wire interface. It employs an open-drain output and is intended
to be wire-OR’d with other devices on the two-wire bus. The input buffer incorporates
a Schmitt trigger for improved noise immunity and the output driver has slope control
for falling edges. An external pull-up resistor is required.
SCL
Input
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL
input also incorporates a Schmitt trigger input for improved noise immunity.
VDD
VSS
Supply Supply Voltage: 5V
Supply Ground
Rev 3.1
May 2005
Page 2 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
