FM24C04A
Address
Latch
128 x 32
FRAM Array
Counter
8
`
Serial to Parallel
Converter
SDA
SCL
Data Latch
WP
A1
Control Logic
A2
Figure 1. Block Diagram
Pin Description
Pin Name
I/O
Pin Description
A1-A2
Input
Address 1-2: The address pins set the device select address. The device address value
in the 2-wire slave address must match the setting of these two pins. These pins are
internally pulled down.
SDA
I/O
Serial Data/Address: This is a bi-directional pin used to shift serial data and addresses
for the two-wire interface. It employs an open-drain output and is intended to be wire-
OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt
trigger for noise immunity and the output driver includes slope control for falling
edges. A pull-up resistor is required.
SCL
WP
Input
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL
input also incorporates a Schmitt trigger input for improved noise immunity.
Write Protect: When WP is high the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.
Input
-
NC
No connect
VDD
VSS
Supply Supply Voltage: 5V
Supply Ground
Rev. 3.0
Mar. 2005
2 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
