FM24C04A
No
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
Data
1
P
By FM24C04A
Acknowledge
Figure 7. Current Address Read
No
Acknowledge
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
A
Data Byte
1
P
By FM24C04A
Acknowledge
Data
Figure 8. Sequential Read
No
Address
Acknowledge
Start
Start
S
Address
Acknowledge
A
By Master
Stop
S
Slave Address
0
A
Word Address
A
Slave Address
1
A
Data Byte
Data Byte
1 P
By FM24C04A
Acknowledge
Data
Figure 9. Selective (Random) Read
defined by A8-A2. Each access causes an endurance
cycle for a row. Endurance is virtually unlimited. At
3000 accesses per second to the same segment, it will
take more than 10 years to reach the endurance limit.
Endurance
Internally, a FRAM operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read or write cycle. The FRAM architecture
is based on an array of rows and columns. Rows are
Rev. 3.2
Feb. 2011
7 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
