Enhanced
Features
Memory Systems Inc.
DM512K32ST/DM512K36ST
512Kb x 32/512Kb x 36 EDRAM SIMM
Product Specification
Architecture
The DM512K36ST
achieves 512K x 36 density by
Actives Pages (Multibank Cache)
mounting five 512K x 8
s
Fast DRAM Array for 30ns Access to Any New Page
s
Write Posting Register for 12ns Random Writes and Burst Writes
EDRAMs, packaged in 44-pin
Within a Page (Hit or Miss)
plastic TSOP-II packages, on
s
1KByte Wide DRAM to SRAM Bus for 56.8 Gigabytes/Sec Cache Fill
a multi-layer substrate. Four
s
On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
2203 devices and one
on Writes
DM2213 device provide data
s
Hidden Precharge and Refresh Cycles
and parity storage. The
s
Extended 64ms Refresh Period for Low Standby Power
DM512K32 contains four
s
Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply
2203 devices for data only.
s
Compatibility with JEDEC 512K x 32/36 DRAM SIMM Configuration
The EDRAM memory
Allows Performance Upgrade in System
module architecture is very
s
Industrial Temperature Range Option
similar to a standard 2MB
DRAM module with the
Description
addition of an integrated
The Enhanced Memory Systems 2MB EDRAM SIMM module
cache and on-chip control which allows it to operate much like a
provides a single memory module solution for the main memory or
page mode or static column DRAM.
local memory of fast embedded control, DSP, and other high
The EDRAM’s SRAM cache is integrated into the DRAM array as
performance systems. Due to its fast 12ns cache row register, the
tightly coupled row registers. The 512K x 32/36 EDRAM SIMM has a
EDRAM memory module supports zero-wait-state burst read
total of four independent DRAM memory banks each with its own 256
operations at up to 50MHz bus rates in a non-interleave configuration x 32/36 SRAM row register. Memory reads always occur from the
and 100MHz bus rates with a two-way interleave configuration.
cache row register of one of these banks as specified by row address
On-chip write posting and fast page mode operation supports
bits A
8
and A
9
(bank select). When the internal comparator detects
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 1KByte cache over a 1KByte-wide bus that the row address matches the last row read from any of the four
DRAM banks (page hit), the SRAM is accessed and data is available
in 18ns for an effective bandwidth of 56.8 Gbytes/sec. This means
on the output pins in 12ns from column address input. Subsequent
very low latency and fewer wait states on a cache miss than a non-
integrated cache/DRAM solution. The JEDEC compatible 72-bit SIMM reads within the page (burst reads or random reads) can continue at
12ns cycle time. When the row address does not match the last row
configuration allows a single memory controller to be designed to
support either JEDEC slow DRAMs or high speed EDRAMs to provide read from any of the four DRAM banks (page miss), the new DRAM
row is accessed and loaded into the appropriate SRAM row register
a simple upgrade path to higher system performance.
and data is available on the output pins
all within 30ns from row enable.
Functional Diagram
Subsequent reads within the page (burst
reads or random reads) can continue at
/CAL
Column
12ns cycle time.
A -A
Address
Latch
Column Decoder
Since reads occur from the SRAM
4 - 256 X 36 Cache Pages
cache, the DRAM precharge can occur
(Row Registers)
4 - 9 Bit
during burst reads. This eliminates the
Comparators
Sense Amps
precharge time delay suffered by other
/G
& Column Write Select
A -A
I/O
DRAMs and SDRAMs when accessing a
4 - Last Row
Control
Read Address
DQ
and
new page. The EDRAM has an independent
Latches
Data
Latches
on-chip refresh counter and dedicated
/S
refresh control pin to allow the DRAM array
Memory
Row
/WE
Array
Address
(2Mbyte + Parity)
Latch
to be refreshed concurrently with cache
read operations (hidden refresh).
During EDRAM read accesses, data
V
C
A -A
can be accessed in either static column
V
/F
Row Adress
s
4KByte SRAM Cache Memory for 12ns Random Reads Within Four
0-3, P
0
7
0
10
0-35
Row Decoder
CC
0
9
1-5
SS
W/R
/RE
0,2
and
Refresh
Control
Refresh
Counter
The information contained herein is subject to change without notice. Enhanced reserves the
right to change or discontinue this product without notice.
© 1996 Enhanced Memory Sytems Inc
, 1850 Ramtron Drive, Colorado Springs, CO
80921
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2113-000
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
