coherency. The EDRAM delivers 12ns cycle page mode memory
writes. Memory writes do not affect the contents of the cache row
register except during a cache hit.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
providing new column addresses to the multiplex address inputs.
New data is available at the output at time tAC after each column
address change. During read cycles, it is possible to operate in
either static column mode with /CAL=high or page mode with /CAL
clocked to latch the column address. In page mode, data valid
time is determined by either tAC or tCQV
.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F & /CAL high. The EDRAM compares the new row address to
the LRR address latch (an 11-bit latch loaded on each /RE active
read miss cycle). If the row address does not match the LRR, the
requested data is not in SRAM cache and a new row must be
fetched from the DRAM. The EDRAM will load the new row data
into the SRAM cache and update the LRR latch. The data at the
specified column address is available at the output pins at the
greater of times tRAC, tAC, and tGQV. It is possible to bring /RE high
after time tRE since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. It is possible to access additional
SRAM cache locations by providing new column addresses to the
multiplex address inputs. New data is available at the output at time
tAC after each column address change. During read cycles, it is
possible to operate in either static column mode with /CAL=high or
page mode with /CAL clocked to latch the column address. In page
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during SRAM cache reads
and maximize SRAM cache hit rate by maintaining valid cache
contents during write operations even if data is written to another
memory page. These new functions, in conjunction with the faster
basic DRAM and cache speeds of the EDRAM, minimize processor
wait states.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table below.
Hit and Miss Terminology
mode, data valid time is determined by either tAC or tCQV.
In this datasheet, “hit” and “miss” always refer to a hit or miss
to the page of data contained in the SRAM cache row register. This
is always equal to the contents of the last row that was read from
(as modified by any write hit data). Writing to a new page does not
cause the cache to be modified.
DRAM Write Hit
If a DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high, the EDRAM will compare the new row
address to the LRR address latch (an 11-bit address latch loaded
on each /RE active read miss cycle). If the row address matches,
the EDRAM will write data to both the DRAM array and selected
SRAM cache simultaneously to maintain coherency. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is
latched by bringing /WE low. The write address and data can be
latched very quickly after the fall of /RE (tRAH + tASC for the column
address and tDS for the data). During a write burst sequence, the
second write data can be posted at time tRSW after /RE. Subsequent
writes within a page can occur with write cycle time tPC. With /G
enabled and /WE disabled, it is possible to perform cache read
operations while the /RE is activated in write hit mode. This allows
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F & /CAL high. The EDRAM compares the new row address to
the last row read address latch (LRR - an 11-bit latch loaded on
each /RE active read miss cycle). If the row address matches the
LRR, the requested data is already in the SRAM cache and no
DRAM memory reference is initiated. The data specified by the
column address is available at the output pins at the greater of
times tAC or tGQV. Since no DRAM activity is initiated, /RE can be
brought high after time tRE1, and a shorter precharge time, tRP1, is
allowed. It is possible to access additional SRAM cache locations by
EDRAM Basic Operating Modes
Function
/S
L
L
L
L
X
/RE
↓
W/R
L
/F
H
H
H
H
L
/CAL /WE
A
Comment
0-10
Read Hit
H
H
H
H
X
X
X
H
H
X
Row = LRR
Row ≠ LRR
Row = LRR
Row ≠ LRR
X
No DRAM Reference, Data in Cache
DRAM Row to Cache
Read Miss
Write Hit
↓
L
↓
H
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
Write Miss
Internal Refresh
↓
H
↓
X
Low Power Standby
Unallowed Mode
H
H
H
H
L
↓
X
X
H
X
H
H
H
X
L
H
X
H
X
X
X
1mA Standby Current
Unallowed Mode (Except -L Option)
Standby Current, Internal Refresh Clock (-L Option)
Low Power Self-Refresh
Option
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
1-20
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
