DM2202/2212 EDRAM
1Mb x 4 Enhanced Dynamic RAM
Product Specification
Enhanced
Memory Systems Inc.
Features
■ 2Kbit SRAM Cache Memory for 12ns Random Reads Within a Page ■ Hidden Precharge and Refresh Cycles
■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ 256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache
Fill
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
on Writes
■ Write-per-bit Option (DM2212) for Parity and Video Applications
■ Extended 64ms Refresh Period for Low Standby Power
■ 300 Mil Plastic SOJ and TSOP-II Package Options
■ +5 and +3.3 Volt Power Supply Voltage Options
■ Low Power, Self Refresh Mode Option
■ Industrial Temperature Range Option
Description
Architecture
The 4Mb Enhanced DRAM (EDRAM) combines raw speed with
The EDRAM architecture has a simple integrated SRAM cache
innovative architecture to offer the optimum cost-performance solution which allows it to operate much like a page mode or static column
for high performance local or system main memory. In most high
speed applications, no-wait-state performance can be achieved without
DRAM.
The EDRAM’s SRAM cache is integrated into the DRAM array as
secondary SRAM cache and without interleaving main memory banks at tightly coupled row registers. Memory reads always occur from the
system clock speeds through 50MHz. Two-way interleave will allow no- cache row register. When the internal comparator detects a page hit,
wait-state operation at clock speeds greater than 100MHz without the
only the SRAM is accessed and data is available in 12ns from column
need of secondary SRAM cache. The EDRAM outperforms conventional address. When a page read miss is detected, the new DRAM row is
SRAM cache plus DRAM memory systems by minimizing processor wait loaded into the cache and data is available at the output all within
states for all possible bus events, not just cache hits. The combination 30ns from row enable. Subsequent reads within the page (burst reads
of data and address latching, 2K of fast on-chip SRAM cache, and
simplified on-chip cache control allows system level flexibility,
or random reads) can continue at 12ns cycle time. Since reads occur
from the SRAM cache, the DRAM precharge can occur simultaneously
performance, and overall memory cost reduction not available with any without degrading performance. The on-chip refresh counter with
other high density memory component. Architectural similarity with
JEDEC DRAMs allows a single memory controller design to support
either slow JEDEC DRAMs or high speed EDRAMs. A system designed in
this manner can provide a simple upgrade path to higher system
performance.
independent refresh bus allows the EDRAM to be refreshed during
cache reads.
Memory writes are internally posted in 12ns and directed to the
DRAM array. During a write hit, the on-chip address comparator
activates a parallel write path to the SRAM cache to maintain
TSOP-II Pin
Configuration
SOJ Pin
Configuration
Functional Diagram
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS *
A
Column
Add
Latch
0-8
/CAL
A
0
2
V
SS
Column Decoder
NC
3
V
SS
512 X 4 Cache (Row Register)
A
1
4
DQ
0
11 Bit
Comp
NC
5
DQ
1
A
V
SS
1
2
3
4
5
6
7
28
27
26
25
0
A
3
6
DQ
2
A
Sense Amps
& Column Write Select
DQ
0
1
/G
A
4
7
NC
DQ
A
DQ
1
3
I/O
Control
and
Data
Latches
NC
8
3
Last
Row
Read
Add
A
DQ
2
4
A
A
5
9
/G
V
0-10
DQ
0-3
A
DQ
3
24
5
/RE
10
11
12
13
14
15
16
17
18
19
20
21
22
CC
/RE
23 /G
V
V
CC
Latch
CC
/S
V
V
CC
22
21
20
19
18
CC
V
V
SS
SS
V
V
SS
8
SS
Memory
Array
(2048 X 512 X 4)
Row
Add
Latch
V
V
SS
SS
A
6
9
/WE
/WE
/S
A
6
/WE
/S
A
7
10
11
12
13
14
A
7
A
8
/F
A
8
/F
A
2
17 W/R
NC
NC
W/R
NC
/CAL
A
9
16
15
/CAL
A
2
V
V
A
CC
CC
10
NC
A
0-9
V
SS
/F
W/R
/RE
Row Add
and
Refresh
Control
A
9
Refresh
Counter
V
A
CC
10
V
NC
CC*
* Reserved for future use
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2107-002
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
