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DM2202J-12 参数 Datasheet PDF下载

DM2202J-12图片预览
型号: DM2202J-12
PDF下载: 下载PDF文件 查看货源
内容描述: [Cache DRAM, 1MX4, 12ns, CMOS, PDSO28]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 19 页 / 156 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号DM2202J-12的Datasheet PDF文件第2页浏览型号DM2202J-12的Datasheet PDF文件第3页浏览型号DM2202J-12的Datasheet PDF文件第4页浏览型号DM2202J-12的Datasheet PDF文件第5页浏览型号DM2202J-12的Datasheet PDF文件第7页浏览型号DM2202J-12的Datasheet PDF文件第8页浏览型号DM2202J-12的Datasheet PDF文件第9页浏览型号DM2202J-12的Datasheet PDF文件第10页  
Switching Characteristics  
V = 5V ± 5% (+5 Volt Option), V = 3.3V ± 0.3V (+3.3 Volt Option), C = 50pf, T = 0 to 70°C (Commercial), -40 to 85°C (Industrial)  
CC  
CC  
L
A
-12  
-15  
Symbol  
Description  
Units  
Min  
Max  
Min  
Max  
(1)  
t
t
t
t
t
t
t
t
t
t
t
Column Address Access Time  
12  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AC  
Column Address Valid to /CAL Inactive (Write Cycle)  
Column Address Change to Output Data Invalid  
Column Address Setup Time  
12  
5
15  
5
ACH  
AQX  
ASC  
ASR  
C
5
5
Row Address Setup Time  
5
5
55  
65  
25  
6
Row Enable Cycle Time  
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only  
Column Address Latch Active Time  
20  
5
C1  
CAE  
CAH  
CH  
Column Address Hold Time  
0
0
5
5
Column Address Latch High Time (Latch Transparent)  
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)  
-2  
-2  
CHR  
t
t
t
t
t
t
t
t
t
0
0
Column Address Latch High to Write Enable Low (Multiple Writes)  
Column Address Latch High to Data Valid  
Column Address Latch Inactive to Data Invalid  
Column Address Latch Setup Time to Row Enable  
/WE Low to /CAL Inactive  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CHW  
CQV  
CQX  
CRP  
CWL  
DH  
15  
17  
5
5
5
0
1
5
5
5
5
5
0
Data Input Hold Time  
1.5  
Mask Hold Time From Row Enable (Write-Per-Bit)  
Mask Setup Time to Row Enable (Write-Per-Bit)  
Data Input Setup Time  
DMH  
DMS  
DS  
5
5
(1)  
GQV  
t
Output Enable Access Time  
5
5
5
5
5
5
(2,3)  
GQX  
t
t
t
t
t
t
t
t
t
Output Enable to Output Drive Time  
0
0
0
0
ns  
ns  
(4,5)  
GQZ  
Output Turn-Off Delay From Output Disabled (/G)  
/F and W/R Mode Select Hold Time  
0
0
ns  
ns  
ns  
ns  
ns  
MH  
5
/F and W/R Mode Select Setup Time  
5
MSU  
NRH  
NRS  
PC  
/CAL, /G, W/R, and /WE Hold Time For /RE-Only Refresh  
/CAL, /G, W/R, and /WE Setup Time For /RE-Only Refresh  
Column Address Latch Cycle Time  
0
0
5
5
12  
15  
(1)  
RAC  
Row Enable Access Time, On a Cache Miss  
30  
15  
35  
17  
ns  
ns  
(1)  
Row Enable Access Time, On a Cache Hit (Limit Becomes t  
Row Enable Access Time for a Cache Write Hit  
Row Address Hold Time  
)
RAC1  
AC  
(1,6)  
t
t
t
30  
35  
ns  
ns  
ns  
RAC2  
RAH  
RE  
1
1.5  
35  
Row Enable Active Time  
100000  
30  
100000  
1-24