are not allowed because a DRAM refresh cycle does not occur when
a read refresh address matches the LRR address latch.
/CAL — Column Address Latch
This input is used to latch the column address and in combination
with /WE to trigger write operations. When /CAL is high, the column
address latch is transparent. When /CAL is low, the column address
latch is closed and the output of the latch contains the address
present while /CAL was high.
Initialization Cycles
A minimum of 10 initialization (start-up) cycles are required
before normal operation is guaranteed. At least eight /F refresh
cycles and two read cycles to different row addresses are necessary
to complete initialization. /RE must be high for at least 300ns prior
to initialization.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
Unallowed Mode
Read, write, or /RE only refresh operations must not be
performed to unselected memory banks by clocking /RE when /S is
high.
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to
/WE — Write Enable
optimize system performance, it is possible to simplify the interface
to the EDRAM by either tying pins to ground or by tying one or
more control inputs together. The /S input can be tied to ground if
the low power standby modes are not required. The /CAL and /F
pins can be tied together if hidden refresh operation is not
required. In this case, a CBR refresh (/CAL before /RE) can be
performed by holding the combined input low prior to /RE. A CBR
refresh does not require that a row address be supplied when /RE
is asserted. The timing is identical to /F refresh cycle timing. The
/WE input can be tied to /CAL if independent posting of column
addresses and data are not required during write operations. In
this case, both column address and write data will be latched by
the combined input during writes. W/R and /G can be tied together
if reads are not performed during write hit cycles. If these
techniques are used, the EDRAM will require only three control
lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and
W/R [combined W/R and /G]). The simplified control interface still
allows the fast page read/write cycle times, fast random read/write
times, and hidden precharge functions available with the EDRAM.
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
DQ — Data Input/Output
0-3
These bidirectional data pins are used to read and write data
to the EDRAM. On the DM2212 write-per-bit memory, these pins
are also used to specify the bit mask used during write operations.
A
0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 9-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
Pin Descriptions
/RE — Row Enable
This input is used to initiate DRAM read and write operations
and latch a row address. It is not necessary to clock /RE to read
data from the EDRAM SRAM row registers. On read operations, /RE
can be brought high as soon as data is loaded into cache to allow
early precharge.
V Power Supply
CC These inputs are connected to the +5 or +3.3 volt power supply.
V Ground
SS
These inputs are connected to the power supply ground
connection.
Pin Names
Pin Names
Function
Pin Names
Function
A
Address Inputs
Row Enable
V
Ground
0-10
SS
/WE
Write Enable
Output Enable
Refresh Control
/RE
DQ
/G
Data In/Data Out
0-3
/CAL
W/R
Column Address Latch
Write/Read Control
Power (+5V or +3.3V)
/F
/S
Chip Select - Active/Standby Control
Not Connected
V
NC
CC
1-22
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
