and data are available. The EDRAM allow 12ns page mode cycle
time for both write hits and write misses. Memory writes do not
affect the contents of the cache row register except during a cache
hit. By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow 4Mb DRAMs.
By eliminating the need for SRAMs and cache controllers, system
cost, board space, and power can all be reduced.
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A (LRR: a 9-bit row address latch for each internal DRAM
bank 2w,9hich is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the column address is available at the output pins at
the greater of times tRAC1, tAC, tGQV, and tASC +tCLV.. Since no DRAM
activity is initiated, /RE can be brought high after time tRE1, and a
shorter precharge time, tRP1, is required. It is possible to access
additional SRAM cache locations by providing new column
addresses to the multiplex address inputs. New data is available at
the output at time tASC +tCLV after each column address change.
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during SRAM cache reads
and maximize SRAM cache hit rate by maintaining valid cache
contents during write operations even if data is written to another
memory page. These new functions, in conjunction with the faster
basic DRAM and cache speeds of the EDRAM, minimize processor
wait states.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
LRR address latch for the bank specified by row address bits A
2,9
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM
cache and a new row must be fetched from the DRAM. The EDRAM
will load the new row data into the SRAM cache and update the
LRR latch. The data at the specified column address is available at
the output pins at the greater of times tRAC, tAC, tGQV, and tASC +tCLV. It
is possible to bring /RE high after time tRE since the new row data is
safely latched into SRAM cache. This allows the EDRAM to
precharge the DRAM array while data is accessed from SRAM
cache. It is possible to access additional SRAM cache locations by
providing new column addresses to the multiplex address inputs.
New data is available at the output at time tASC +tCLV after each
column address change.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table below.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A and A . The contents of these cache row
9
registers is always equal 2to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
Four Bank Cache Architecture
Bank 3
Bank 2
Bank 1
Bank 0
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
CA
0-8
D0-35
1MB Array
1MB Array
1MB Array
1MB Array
A
Data-In
Latch
0-10
512 x 36
Cache
512 x 36
Cache
512 x 36
Cache
512 x 36
Cache
CA
0-8
Bank 0
Bank 1
Bank 2
Bank 3
(0,0)
(0,1)
(1,0)
(1,1)
1 of 4 Selector
RA , RA
2
9
Data-Out
Latch
CAL
G
S
Q 0-35
2-76
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
