P4C1024L - LOW POWER 128K X 8 CMOS STATIC RAM
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
3ns
Mode
CE1 CE2 OE WE
I/O
Power
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
Standby
H
X
L
L
L
X
L
X
X
H
L
X
X
H
H
L
High Z Standby
High Z Standby
High Z Active
DOUT Active
1.5V
Standby
DOUT Disabled
Read
1.5V
H
H
H
See Fig. 1 and 2
Write
X
DIN
Active
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
To avoid signal reflections, proper termination must be used; for example,
a 50Ω test environment should be terminated into a 50Ω load with 1.77V
(Thevenin Voltage) at the comparator input, and a 589Ω resistor must be
used in series with DOUT to match 639Ω (Thevenin Resistance).
Because of the high speed of the P4C1024L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground.
Document # SRAM125 REV G
Page 6
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
