P4C1024L - LOW POWER 128K X 8 CMOS STATIC RAM
DATA RETENTION
Symbol Parameter
Test Conditions
Min Max Unit
CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
VDR
VCC for Data Retention
2.0
5.5
V
VDR = 2.0V
20
30
µA
µA
ns
(1)
ICCDR
Data Retention Current
VDR = 3.0V
tCDR
tR
Chip Deselect to Data Retention Time
Operating Recovery Time
See Retention Waveform
0
5
ms
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED)
LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED)
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR
tCDR
tR
VIL
CE2
VIL
2.2V
CE2 -0.2V
Document # SRAM125 REV G
Page 7