P4C1024L - LOW POWER 128K X 8 CMOS STATIC RAM
READ CYCLE NO. 1 (OE CONTROLLED)(1)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CECONTROLLED)
Notes:
1. WE is HIGH for READ cycle.
4. Transition is measured ± 200 mV from steady state voltage prior to
change,withloadingasspecifiedinFigure1. Thisparameterissampled
and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE1 transition LOW or CE2 transition HIGH.
Document # SRAM125 REV G
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