P4C1023/P4C1023L
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
TRUTH TABLE
AC TEST CONDITIONS
I/O
High Z
High Z
DOUT
Power
Standby
Active
Mode
Standby
DOUT Disabled
CE OE WE
Input Pulse Levels
GND to 3.0V
H
L
L
L
X
H
L
X
H
H
L
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
Read
Write
Active
Active
X
DIN
See Figures 1 and 2
* including scope and test fixture.
Note:
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with DOUT to match 639Ω
(Thevenin Resistance).
Because of the high speed of the P4C1023L, care must be taken when
testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground.
Document # SRAM126 REV OR
Page 6 of 11
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