P3C1256L - 32K x 8 STATIC CMOS RAM
TIMIꢀꢂ WAVEFORM OF READ CꢄCLE ꢀO. 1 (OE COꢀTROLLED)(5)
TIMIꢀꢂ WAVEFORM OF READ CꢄCLE ꢀO. 2 (ADDRESS COꢀTROLLED)(5,6)
TIMIꢀꢂ WAVEFORM OF READ CꢄCLE ꢀO. 3 (ADDRESS COꢀTROLLED)(5,7)
ꢀotes:
1. Stresses greater than those listed under MAꢀIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAꢀIMUM rating conditions for extended
periods may affect reliability.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change,withloadingasspecifiedinFigure1. Thisparameterissampled
and not 100% tested.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
Document # SRAM143 REV A
Page 4
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
