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P3C1041-20JI 参数 Datasheet PDF下载

P3C1041-20JI图片预览
型号: P3C1041-20JI
PDF下载: 下载PDF文件 查看货源
内容描述: 高速256K ×16 ( 4 MEG )静态CMOS RAM [HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM]
分类和应用:
文件页数/大小: 10 页 / 291 K
品牌: PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
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P3C1041  
TIMING WAVEFORM OF READ CYCLE NO. 1  
TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)(5,6)  
Notes:  
1. Stresses greater than those listed under MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification  
is not implied. Exposure to MAXIMUM rating conditions for extended  
periods may affect reliability.  
4. This parameter is sampled and not 100% tested.  
5. WE is HIGH for READ cycle.  
6. CE is LOW and OE is LOW for READ cycle.  
7. ADDRESSmustbevalidpriorto,orcoincidentwithCE transitionLOW.  
8. Transition is measured ± 200 mV from steady state voltage prior to  
change, with loading as specified in Figure 1. This parameter is  
sampled and not 100% tested.  
2. Extended temperature operation guaranteed with 400 linear feet per  
minute of air flow.  
3. Transient inputs with VIL not more negative than –2.0V and  
9. Read Cycle Time is measured from the last valid address to the first  
transitioning address.  
VIH VCC + 0.5V, are permissible for pulse widths up to 20ns.  
Document # SRAM130 REV OR  
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