PACE1753/SOS
SINGLE CHIP, MIL-STD-1750A
MEMORY MANAGEMENT UNIT (MMU)
CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture for Memory Management and
Protection of up to 1 Megaword. All mapping
memory (10,240 bits) for both the MMU and
BPU functions are included on the chip.
Designed to interface memory to the
PACE1750A/AE.
Provides the following additional functions:
— EDAC, Error Detection and Correction—or
parity generation and detection
— Correct data register—for diagnostics
— First memory failing address register
— Illegal address error detection—
programmable
— Multi-Master arbitration
8-bit extended address laches and drivers on
chip.
20, 25 and 30 MHz operation over the Military
Temperature Range
Single 5V ± 10% Power Supply
Available with Class S manufacturing,
screening, and testing.
SOS Insulated substrate latch-up immunity and
excellent SEU tolerance.
SOS devices are fully interchangeable with
application-proven SMD CMOS P1753 devices.
Available in:
— 68-Lead Quad Pack (Leaded Chip Carrier)
with optional Gull Wing.
MEMORY MANAGEMENT UNIT AND
BLOCK PROTECT UNIT “COMBO”
(PACE1753)—FUNCTIONAL DESCRIPTION
The PACE1753 (COMBO) is a support chip for the
PACE1750A/AE microprocessor family. It provides the
following supporting functions to the system:
1. Memory management and access protection for up
to 1M words.
2 Physical memory write protection for up to 1M words
memory in pages of 1K words each. Separate
protection is provided for the CPU and for DMA in
systems which include DMA.
3. Detection of illegal l/O accesses (as defined by MIL-
STD-1750A) or access to an unimplemented block
of memory. In each case an error flag is generated
to the processor.
4 Detection of double errors on the data bus and
correction of single errors. An error signal is generated
to the processor when a multiple error is detected.
5. RDYA generation. Up to three wait states can be
inserted in the address phase of the bus by generating
a not-ready, RDYA low signal. The number of wait
states required can be programmed in an internal
register in the COMBO.
6. Bus arbitration for up to 4 masters. Arbitration is
done on a fixed priority basis (i.e. by interconnection
of hardware). (In 68 pin package only).
Document #
MICRO-8
REV B
Revised August 2005
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
