PACE1753
AC ELECTRICAL CHARACTERISTICS
(V = 4.5V)
CC
20 MHz
30MHz
40 MHz
Symbol
Parameter
MMU Cache Hit
TSTRBD (EXT ADR ERR) External Address Error
Min Max Min Max Min Max Unit
TD/I (EXT ADR)
25
25
23
20
23
16
ns
ns
V
L
TC (IBD CORR)
IBD (SING ERR)
Error Correction Read Cycle
Error Correction Read Cycle
25
35
20
30
19
25
ns
ns
V
H
TC (SING ERR)
Error Correction Read Cycle
EDAC or Parity Write Cycle
MMU Cache Miss
25
30
25
25
25
25
35
35
35
35
30
30
34
50
25
25
25
50
40
45
25
32
20
25
20
20
22
20
25
25
25
25
25
28
30
45
20
22
22
45
35
35
20
30
12
23
12
12
18
16
18
18
18
18
17
25
25
40
16
18
18
40
30
30
20
23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
TIBD (EDC GEN)
V
V
TSTRBD (EX RDY)
L
TC (EX RDY)
MMU Cache Miss
H
TC (WR PROT)
MMU Cache Miss
L
TSTRBD (WR PROT)
MMU Cache Miss
H
H
TC (GNT1)
TC (GNT0)
TC (GNT0)
TC (GNT1)
Arbiter LOW to HIGH Priority
Arbiter LOW to HIGH Priority
Arbiter HIGH to LOW Priority
Arbiter HIGH to LOW Priority
Address Ready
H
L
H
L
TC (RDYA)
TFC (IB OUT)
Clock to IB Out Valid (I/O Read)
Parity Mode
V
TIBD (MEM PAR ERR)
IN
TC (MEM PRT ERR)
TSTRBD (WR PROT)
Memory Protect Error
Write Protect Cache Hit
Write Protect Cache Miss
Write Protect Cache Miss
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Cache Miss (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Clock to EXT ADR Valid (Miss)
TC (WR PROT)
L
TSTRBD (WR PROT)
H
H
TD/I (PROT FLAG)
TD/I (PROT FLAG)
TC (PROT FLAG)
TC (PROT FLAG)
TC (EXT ADR)
Notes:
1. 4.5V ≤ V ≤ 5.5V, –55°C ≤ T ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
CC
C
2. V = –3.0V for pulse widths less than or equal to 20ns.
IL
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
4. Pulse width of WR PROT/PROT FLAG shall be ≥ 80% of STRBD pulse width.
Do c um e nt # MICRO-4 REV D
Pa g e 4 o f 21
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
